Custom Logic With Address Decoding

For address decoding on your 6502 what your probably want is not even a CPLD but just a plain old PLD. However, a modern CPLD may be easier to work with, even though it's overkill. The xilinx PLD starter kit might not be bad... there FPGA starter kit is great, but an FPGA is overkill and often takes more support circuity than you'd want to include. Choose your PLD by compatibility with your logic voltage, package type that you can work with, ease of programming/programmer expense, and quality of toolset.

A PIC is totally the wrong choice. Address decoding is a simple task for dedicated logic, regardless if it is hard wired or a sea of gates wired up by soft programmable "wires" - it's not a job for a sequential processor. If you want to use a PIC, why not run your program in the PIC rather than the 6052?

But there may be a far simpler and cheaper to work with solution: do you need to efficiently use the whole address space? Or can you afford to waste space by incompletely decoding the addresses, such that a given device may show up at numerous addresses or that larger blocks of space may be unused? Classic chips like the 74xx138 are great for this 3 address lines in, plus some additional enables, and 8 decoded chip selects out. You can even use two of them in series to divide things finer. For example with a 64k address space, one '138 gets you

There's another size of programmable logic device that fits below CPLDs. Nowadays, that niche is mostly filled by GAL devices (16V8, 22V10), although there were PAL devices and other varieties in the not too distant past.

The devices are affordable and there are free "compilers" (used loosely) for them, e.g., winCUPL available from Atmel.

The problem that you may run into is that most of them (at least, all that I know of) require device programmers to burn the JEDEC file onto the device. If you already have one, you're done. Pick up some ATF16V8CZ or ATF22V10CZ devices from Digikey, the datasheets and CUPL environment from Atmel. The CUPL language is fairly straightforward and well suited to small devices like GALs.

If you don't already have a programmer, commercial ones run from about $250 and up. There may be "roll yer own" plans on the 'net.

A small CPLD might be a fit. Generally you'll develop the program in a hardware description language (Verilog, VHDL, ...) or via schematic capture. One benefit is that, for the most part, available CPLDs are programmed via a JTAG interface and those programmers are much, much cheaper than a "universal" programmer that you'd probably need if you aimed for a GAL device. Xilinx and Altera are major players and both have free development environments (ISE Webpack and Galaxy, IIRC).

Another possibility is the "smallest" programmable logic family: a PROM (EEPROM, flash ROM, etc.). The data selected by the address lines is programmed to match the desired logic, e.g., only THIS address asserts THAT output-enable bit. You may need a separate D-flipflop to latch the data, though.

The advantage of programmable logic is that it doesn't need to go through the microcontroller's fetch-decode-act logic loop; you avoid all of the "read this port, if the value is whatever, then set this bit on the other port" which may consume several 10s of microseconds, whereas the programmable logic devices will typically have input to output times on the order of 10s of nanoseconds.

If it's a one-off, if you already have the parts, and if the propagation delay is acceptable, then it's probably reasonable to stick with a PIC for now. It wouldn't hurt to expand your toolkit, though, and pick up (no pun intended) a dev board and a JTAG cable and get familiar with programmable logic devices.

In my case it'd be good'ol DIP at 5v for logic. Unfortunately, my Willem programmer apparently lacks the ability for any of those sort of devices. I'm just a hobbyist, so unless I could find a programmer relatively cheap, they might be out of my league for now. The actual PLDs themselves seem that they might be cheaper than PICs, though.

The project is actually interfacing with a seperate 6502-powered device, so even though the primary job would be address decoding, I figured the PIC would also allow for some expandability in regards to features later on, like being able to write to it to actually change the address decoding on the fly.

Since it's interfacing another device, it already has its preset memory map, which I'm wanting to squeeze things into the gaps of in the places where it doesn't mirror, as well as using its standard rom/ram address space. The smaller gaps are for inserting registers for a floppy controller, for example, which would mean address decoding resolution down to like 128-256 bytes preferably. My original design with logic chips involved a full ls139, an inverter (using only a couple from it), and a couple quad ORs (using nearly all). This setup would decode most of what I had in mind in terms of those address gaps, but again, that's a lot of wiring if one can avoid it with some other trick.

I'm not against doing it the hard way of course, it was just the thought of later possibly implementing an easy rom bank-switching solution with a PIC that got me wondering if it could handle the speed.

Check out "in-system programmable" (ISP) PLD's. Altera and Lattice are probably the manufacturers to look at. These days even Xilinx offers some ISP parts.

A PLD e.g. 16V8 or 22V10 would be my first choice. I bought a cheap Xeltek Superpro Z programmer for these. You can get PLD programmers on eBay. If more pins or more macrocells were required, I would use a CPLD e.g. Altera EPM7064. You can get a Byte-Blaster cable on eBay to program these. The development software is free, and you just need a 10-way JTAG header for connecting the cable to your target system. This also enables re-programming later. The CPLD is programmed whilst in-cicuit.

If the OP chooses to use an FPGA, he might as well include the 6502 inside the FPGA and have it run at 100MHz :-)

Virtually everything from CPLD up is ISP from all the major vendors nowadays, with pretty app notes (and sample code) to show you how. You don't need any homebrew code if you use the free tools and the cable from the vendors - I seem to remember there was a schematic floating around for the byteblaster a while back, though.

I don't know the cost for the byteblaster as it's been a while since I used one, but the Xilinx programmer cable (parallel IV is the current incarnation) is about =A350/$99 depending on where you get it. Probably available on ebay for a lot less.

If you use that, download the Webpack (warning - full install is ~100MByte!). I think they will send it to you on a CD for some nominal cost.

Even a small CPLD would be overkill, but as you want future options, it might not be a bad choice. The Altera (via byteblaster) and Xilinx (via parallel programmer) support InSystem options (just bring the JTAG port to a suitable header), so it's easy to update.

Cheers

PeteS

How many bits? Generally the MSI function specific logic chips come in

In article , PeteS wrote: [...]

You don't even need a Byteblaster if you have a PC that lets you get at the printer port. A ribbon cable and 4 resistors works from the MAX7000 parts.

You make a JAM file with Quartus and then run a Jam/Staple player. I have a modified one, I'd be willing to share that works on Linux.

As other people have said, you definitely don't want a PIC. In keeping with the 6502 era technology, a GAL, PAL or EPROM would be suitable, but they will require specialized programming hardware.

A CPLD will do what you want, and you can build a programmer from parts you already have. Xilinx and Altera both have free software, and I know for sure that the Xilinx tools will allow you to design your part with schematic capture using arbitrary gates or even 7400 series equivalent blocks. So if you are comfortable drawing a multi-chip solution on paper, you can generate a bitstream for a CPLD without much learning curve. You can even try it with no hardware at all.

The sort of parts you want to consider are the Xilinx XC9500 series (5V with 5V IO) or similar vintage with 3.3V core and 5V tolerant IO. The XC9536 in PC44, for example, can probably handle all the address decoding for an entire C64-like computer.

If you've got 3.3V supply handy, the Altera MAX EPM3032A is 5V tolerant and has similar capability. I think they're around $1.25 from Digikey.

PAL is/was often used for address decoding.

way too slow look at the timing constraints of the 6502

That said, the code in either Verilog or VHDL for a simple address decoder is hardly complex, and would also introduce the OP to a new area :)

Cheers

PeteS