Xilinx XC9500 CPLD Wired-OR; Wired-ND

The one I can think of:

if OR_REDUCE(drivers) = '1' then w

Thanks for the help valentin.

I want to use the Xilinx XC9536. If I use a pull-down resitor, I can do a Wired-OR with several pins, right?

Bruno

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I think, yes. You'll pull the line up by resistor (several kilos?). CPLD will drive either '0' or 'Z'. When all 'Z' than line is high, it will be 0 otherwise. The same can be applied to pull-down resistor and '1', 'Z' drivers. Line will be zero when nothing drives it. If CPLD outputs support 'Z' state then I see no problem.

right?

If you want reasonable speed, then use 470 Ohm (10 mA @ 5V) or even at 3.3 V. Higher resistors give long risetime. If that is acceptable, you can use something like 5.6 k. Peter Alfke

I meant to write: ... or even 330 Ohm at 3.3 V... Peter ===========

OK. Lots of responses already to your problem.

A small remark regarding the use of strong pullups or pulldown resistors: they are of course required if you need speed and may not integrate more complex logic, but are power hungry. Obvious !

However, I had a problem like that one day, and solved it differently.

If the output pins you want to wire-or may be driven by a sequential state machine AND no contention can occur (by definition of the problem for instance), it is not difficult to build a state machine that drives the wire-or bus 1 or more clocks at the value required, and finally ends up by driving the bus to its rest (idle) state for 1 more clock (even maybe half a clock).

Then, idle state is kept by weak pullups or pulldowns or keeper circuits if any.