Hi. i wanted a help from this group.i'am currently working on synthesis and

need some articles or material how to proceed with the synthesis. for example.. once we have designed a vhdl code. verified the output in testbench. how do we proceed next. synthesis is the next step if 'am not wrong. we get the synthesis report.. but if i get info on how synthesis is done and the design flow, explaiing the steps to be performed explaiing how to carry out till the

design is ported on the hardware. so i can learn and get more idea on the same..

Thanks in advance. HOPE TO GET A GOOD RESPONSE... chears


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The synthesis should be done by the tools that you are using. The synthesis process converts the high level VHDL code into a lower level (standard?) form that can be used by the device fitter to implement the logic. An example of synthesis output would be a set of sum of product equations. One reason to use tools is that they should take care of this for you automatically in addition to performing the minimization and optimization for you. Another reason to use a tool is that the form of the best fit will be device specific depending on the resources available in the device.

What development tool platform are you working with and what is your target device?

This is unless your assignment is to hand synthesize the code as part of an assignment in a VLSI or some other class. .

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my target device is Spartan3, xc3s400.

i'am an intern in a company and have developed many small projects and currently studying how to use synthesis. thought if i can get links wer the steps are mentioned in which i can learn how to synthesise my code.

thanks Bye

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I "normally" use Altera devices. I have a personal preference for them over Xilinx in addition to a poor technical experience with their XC9500 series PLDS.

I would assume that you are either using a set purchased development tools or their webpack ISE. EIther one should have a synthesis step as part of the compile or build process.

As I indicated, the synthese process converts the VHDL code into a format applicable to the logic family. The synethesizer must be aware of the resources available in the device, e.g. how many global clock buffers are available, or are global resets available, etc.

If you are interested in the nuts and bolts of synthesis, a good place to start may be in compiler algorithms as this is basically what the synethizer is.

Hope my explanation helps.

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well, the synthesis report mentions everything, how many gclk, slices, lut's, multipliers.. according to that we have to modify the design.

i dint actually understand by what you said regarding compiler algorithms ... actually i was thinking of getting an idea the steps from coding till porting the code in the hardware.. if i can get this info on net... any material which will explain step by step after the coding and testing of the code in testbench till porting it on hardware.

would be very greatful if u can suggest me with any link of a pdf file that can solve my problem...

thanks TAKE CARE

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Abbs schrieb:

Hi Abbs, if I understand your question right, you are wondering what the synthesis tool is making out of your source code. And you want to know this before synthesis, so you can estimate the effects of your source code on the synthesis result.

Well, there's the IEEE synthesis standard for vhdl (IEEE 1076.6)that explains in detail what kind of hardware is generated from a synthesizable statement. This information is not vendor specific, and the synthsis tools often make use of vendor specific features when applicable, but it's a good start point.

Another important thing is the setting of the synthesis tools options. e.g. in XST you can choose how many Clockbuffers should be used and wether BRAMS schould be used for logic or not and much more. Study these options and if you are still in doubt about some of your result put that small part of your project in a separated project and study the efffects of different coding styles and/or options by looking ath the RTL and Technology schematics created by the synthesis tool (the 7.1 rtl view sometimes misses to plot some inverters though) and compare these results. There's a lot to learn...

have a nice synthesis Eilert

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