Field-Programmable Gate Arrays

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How could I get LUT-level netlist in Xilinx ISE?

Hi, I need to convert the high level design to LUT level netlist, and then make corrections to it. "The translate step...
7 comments posted 15yrs
posted by eric.he
7 comments posted 15yrs posted by eric.he

Microblaze and PowerPC

Hi, I would like to perform mathematical operations as Division and Square root. From what i have read, i either need t...
3 comments posted 15yrs
posted by ammarei
3 comments posted 15yrs posted by ammarei

FFT using logic gates only

I intend to implement FFT using Logic gates only , by this i mean i have written verilog code of FFT for xilinx spartra...
9 comments posted 15yrs
posted by moindsp2011
9 comments posted 15yrs posted by moindsp2011

Random Reset calls

Hi Folks, Need something interesting in random reset: I am having a testbench in verilog which needs to hit the state m...
1 comments posted 15yrs
posted by rsgupta.gupta
1 comments posted 15yrs posted by rsgupta.gupta

Package constants (VHDL)

Historically I have used a VHDL file to embody the constants in a design where possible using meaningful names which ca...
2 comments posted 15yrs
posted by fred__bloggs
2 comments posted 15yrs posted by fred__bloggs

please see me

snipped-for-privacy@rediffmail.com
0 comments posted 15yrs
posted by mveni.nirmala
0 comments posted 15yrs posted by mveni.nirmala

Call for Papers (CFP)

========================================================= ARPN Journal of Systems and Software Call for Research Papers...
0 comments posted 15yrs
posted by saeedullah81
0 comments posted 15yrs posted by saeedullah81

Records as ports in Synplify

We are trying to implement a toplevel module which has an IN and an OUT port which are records. The synthesis works fin...
0 comments posted 15yrs
posted by miguel.cholbicollados
0 comments posted 15yrs posted by miguel.cholbicollados

PCI Express Cable

Hi, Does anybody here have experience designing something to do PCIe over cable? I need to design (ie, draw the schemat...
10 comments posted 15yrs
posted by jjlarkin
10 comments posted 15yrs posted by jjlarkin

Fall Times and Pullup

If on a bidirectional bus, if there is a strong pull up and there is a device which is drives the line low, can we redu...
9 comments posted 15yrs
posted by mail.ghanashyam.prabhu
9 comments posted 15yrs posted by mail.ghanashyam.prabhu

comparator fast implementation

Hi, In my design i have two counters, a write_counter and a read_counter, both are 11 bits wide. I used a simple compar...
5 comments posted 15yrs
posted by a1234573
5 comments posted 15yrs posted by a1234573

Problem with Xilinx 10.1 PowerPC simulator

Hi, I'm trying to use Xilinx 10.1 SDK for PowerPC simulation. However for = unknown reasons SDK is unable to connect to...
2 comments posted 15yrs
posted by opti
2 comments posted 15yrs posted by opti

Quadrature Modulation Tutorial

I have made a tutorial using flash programs that will help you understand how quadrature modulation and quadrature demo...
2 comments posted 15yrs
posted by bulegoge
2 comments posted 15yrs posted by bulegoge