Latest threads in Field-Programmable Gate Arrays

verilog task and vhdl

Hi all, I've a functional model of a PHY chip in verilog with a lot of tasks to stimualte change on signals at the inte...

10 15yrs

carlo.beccia

10 15yrs carlo.beccia

Connecting of IP core simulated in GHDL to pseudoterminal via UART-like interface

When working with simulated soft CPUs to be implemented in FPGA, I often needed a possibility to connect terminal emula...

2 15yrs

wzab

2 15yrs wzab

How could I get LUT-level netlist in Xilinx ISE?

Hi, I need to convert the high level design to LUT level netlist, and then make corrections to it. "The translate step...

7 15yrs

eric.he

7 15yrs eric.he

Microblaze and PowerPC

Hi, I would like to perform mathematical operations as Division and Square root. From what i have read, i either need t...

3 15yrs

ammarei

3 15yrs ammarei

FFT using logic gates only

I intend to implement FFT using Logic gates only , by this i mean i have written verilog code of FFT for xilinx spartra...

9 15yrs

moindsp2011

9 15yrs moindsp2011

Random Reset calls

Hi Folks, Need something interesting in random reset: I am having a testbench in verilog which needs to hit the state m...

1 15yrs

rsgupta.gupta

1 15yrs rsgupta.gupta

Package constants (VHDL)

Historically I have used a VHDL file to embody the constants in a design where possible using meaningful names which ca...

2 15yrs

fred__bloggs

2 15yrs fred__bloggs

please see me

snipped-for-privacy@rediffmail.com

0 15yrs

mveni.nirmala

0 15yrs mveni.nirmala

Call for Papers (CFP)

========================================================= ARPN Journal of Systems and Software Call for Research Papers...

0 15yrs

saeedullah81

0 15yrs saeedullah81

Instantiation of an EDF netlist within a Verilog top RTL

Hello Guys, I am working with Synplify Pro. I have a RTL wrapper in Verilog where a module is instantiated. But this mo...

2 15yrs

rahulece83

2 15yrs rahulece83

Records as ports in Synplify

We are trying to implement a toplevel module which has an IN and an OUT port which are records. The synthesis works fin...

0 15yrs

miguel.cholbicollados

0 15yrs miguel.cholbicollados

PCI Express Cable

Hi, Does anybody here have experience designing something to do PCIe over cable? I need to design (ie, draw the schemat...

10 15yrs

jjlarkin

10 15yrs jjlarkin

HEART 2011, June 2-3 2011, Imperial College London, Call for Participation

Dear Colleagues, We cordially invite you to join us at the 2nd International Workshop on Highly Efficient Accelerators...

0 15yrs

k.benkrid

0 15yrs k.benkrid

Fall Times and Pullup

If on a bidirectional bus, if there is a strong pull up and there is a device which is drives the line low, can we redu...

9 15yrs

mail.ghanashyam.prabhu

9 15yrs mail.ghanashyam.prabhu

comparator fast implementation

Hi, In my design i have two counters, a write_counter and a read_counter, both are 11 bits wide. I used a simple compar...

5 15yrs

a1234573

5 15yrs a1234573

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