Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Problem with Xilinx 10.1 PowerPC simulator
Hi, I'm trying to use Xilinx 10.1 SDK for PowerPC simulation. However for = unknown reasons SDK is unable to connect to debugger. This is a dump = from XMD console: Accepted a new TCLSock connection...
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12 years ago
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Quadrature Modulation Tutorial
I have made a tutorial using flash programs that will help you understand how quadrature modulation and quadrature demodulation works. It is located here: I try to show you without getting bogged down...
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12 years ago
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Can a glitch-free mux be designed in an FPGA?
Hi: The simplest incarnation of a 2-to-1 multiplexer can be described by the equation: y = ~s & a | s & b where 'y' is the output, 's' is the select input, with 'a' and 'b' the data inputs. Of course,...
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12 years ago
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Problem with xilinx 12.3 Timing Analyzer
Hi, I am using xilinx 12.3 for my synthesis and implementation. I am having issues running timing analyzer, the problem is that when i run timing analyzer from the ISE Design Tools menu as a stand...
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12 years ago
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AVI container and VGA display
hi all! I'm working on the Spartan 3E started with mapping MJPEG decoder. I had the source code of the JPEG deccoding, now I use AVI container to display MJPEG via VGA port. I wanna find the first...
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12 years ago
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Verify failed between address 0x80000 and 0x8FFFF
Hello, I've been attempting to basically run through the mem_test template and tutorial,on Cyclone® III EP3C120 chip board. I am able to compile the custom SOPC design, the encompassing Quartus file,...
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12 years ago
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Re: How to use the EXT_CLK_P and EXT_CLK_N pins of Virtex II Pro (XC2VP30, package ff896) ?
AST | LEW Sorry...The link for the picture was wrogly pasted...Here is the correct link.
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12 years ago
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Modelsim
Does anyone know if its possible to change the waveform signals so that they are in hex instead of binary. I dont want to do it manually but just have it come up in hex when the design is loaded....
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12 years ago
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Scoping a glitch
Hi: Today I took scope shots of a clock input to my Xilinx Spartan 3e, Digilent NEXYS2 board. The clock goes to a counter, simulating a quadrature encoder, as explained in post "Counter clocks on both...
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12 years ago
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please see me
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12 years ago
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Random behavior of xilinx simple dual port block ram
Hi, I am using xilinx 12.3 for synthesis and implementation of my design and i am facing 2 problems. I don't know if anyone else has faced them or not. Problem 1: I am using xilinx simple dual port...
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12 years ago
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spartan 3a ethernet
for this project, things need to be changed in order to make it work in spartan 3a? regards --------------------------------------- Posted through
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12 years ago
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Counter clocks on both edges sometimes, but not when different IO pin is used
Hi: I'm using a Xilinx Spartan 3E FPGA (on the Digilent NEXYS2 500k board) to implement a quadrature encoder simulator, among other things. The qep_sim.v code is shown below. The clock input to...
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12 years ago
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Best syntheses
Hi, I have been using Xilins XST for a while and have come to a performance problem which leads me to think of if there is any better syntheses like Synopsys or other. The device is a Spartan3 4000 an...
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12 years ago
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J1 forth processor in FPGA - possibility of interactive work?
Hi, I'm very impressed with a J1 forth processor: 'd like to use it to implement simple non-time critical control and debugging layer in my FPGA based DSP system. However to accomplish it I need to...
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12 years ago
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