Latest threads in Field-Programmable Gate Arrays

How to open the interface GUI of ChipScope Pro Analyzer on linux

Hi, I want to using ChipScope Pro Analyzer to check my design. I have already generated the icon and ila cores and conn...

2 15yrs

lijing8898

2 15yrs lijing8898

Verilog Custom Core To Read and Write From RAM

I want to add a custom verilog core to an already established pipeline of microblaze. The core should be able to read d...

8 15yrs

aibk01

8 15yrs aibk01

Xilinx ISE ignores Max Fanout

I had been working with Xilinx ISE 12.4 for a while trying to improve the performance of a SPARC based processor. Till...

0 15yrs

arjunsha

0 15yrs arjunsha

ucf file for 32 bit counter spartan 3e S500E -4

I have designed a 32 bit counter but I am having a difficulty in assigning 32 pins to the 32 bits since I don't know th...

2 15yrs

hi.maddy08

2 15yrs hi.maddy08

[OT] How to save an artifical life..

Hi everyone, I would like to share a youtube clip...one click costs nothing while can save lives sometimes (expecially m...

0 15yrs

davcori

0 15yrs davcori

Sporadic simulation result with modelsim

Hello all, I struggle with an issue I can't understand the root cause. When simulating my back annoted design with mode...

20 15yrs

jb.dubois.jbd

20 15yrs jb.dubois.jbd

Xilinx or Altera

Hopefully not sparking any religious wars here, but hoping for some advice from those-who-know :) I switched to using A...

15 15yrs

google

15 15yrs google

Choosing a scope

Hello, I am trying to choose a new oscilloscope, but also keeping my eye on logic analyzers. I am mostly working with v...

4 15yrs

hidden

4 15yrs hidden

Determine latency of GTX links vs Aurora+LVDS

I have a design partitioned over 2 FPGAs. I am trying to determine the bene= fits of selecting GTX links vs. LVDS to tr...

3 15yrs

vivek.menon79

3 15yrs vivek.menon79

Area optimization (optimizing DSP48E usage)

I am trying to map, place & route a large design on a Xilinx Virtex 6 FPGA Target Device : xc6vlx550t Target Package :...

1 15yrs

vivek.menon79

1 15yrs vivek.menon79

What is the advantage of source-syncronization (in SDRAMs)?

The data arrives with some unknown phase shift relatively to system (synchronized to SDRAM) clock. DQ can be captured m...

19 15yrs

intellij

19 15yrs intellij

Area Optimization

Hi all, I have a design (written in VHDL) targetting the Spartan 6 series, and it's oversubscribed for LUTs. Can anyone...

24 15yrs

chead

24 15yrs chead

Variable Optimized Away

Hello, I am having a problem where Xilinx ISE is trimming away a variable that I need, tempShifts. I can still implemen...

5 15yrs

ballcalvin

5 15yrs ballcalvin

multiplication in indexation

Hello everyone I want to do a for loop in order to repeat the same construction and use the number of the loop to creat...

3 15yrs

alexis.gabin

3 15yrs alexis.gabin

Looking for bitgen Virtex7 and Kintex7 support

Hello, It appears that bitgen in ISE 13.1 supports Virtex7 and Kintex7 implementation up to but not including bitstream...

3 15yrs

neil.steiner

3 15yrs neil.steiner

Field-Programmable Gate Arrays

Worth reading in Field-Programmable Gate Arrays