Field-Programmable Gate Arrays

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Xilinx ISE ignores Max Fanout

I had been working with Xilinx ISE 12.4 for a while trying to improve the performance of a SPARC based processor. Till...
0 comments posted 15yrs
posted by arjunsha
0 comments posted 15yrs posted by arjunsha

ucf file for 32 bit counter spartan 3e S500E -4

I have designed a 32 bit counter but I am having a difficulty in assigning 32 pins to the 32 bits since I don't know th...
2 comments posted 15yrs
posted by hi.maddy08
2 comments posted 15yrs posted by hi.maddy08

[OT] How to save an artifical life..

Hi everyone, I would like to share a youtube clip...one click costs nothing while can save lives sometimes (expecially m...
0 comments posted 15yrs
posted by davcori
0 comments posted 15yrs posted by davcori

Sporadic simulation result with modelsim

Hello all, I struggle with an issue I can't understand the root cause. When simulating my back annoted design with mode...
20 comments posted 15yrs
posted by jb.dubois.jbd
20 comments posted 15yrs posted by jb.dubois.jbd

Xilinx or Altera

Hopefully not sparking any religious wars here, but hoping for some advice from those-who-know :) I switched to using A...
15 comments posted 15yrs
posted by google
15 comments posted 15yrs posted by google

Choosing a scope

Hello, I am trying to choose a new oscilloscope, but also keeping my eye on logic analyzers. I am mostly working with v...
4 comments posted 15yrs
posted by hidden
4 comments posted 15yrs posted by hidden

Determine latency of GTX links vs Aurora+LVDS

I have a design partitioned over 2 FPGAs. I am trying to determine the bene= fits of selecting GTX links vs. LVDS to tr...
3 comments posted 15yrs
posted by vivek.menon79
3 comments posted 15yrs posted by vivek.menon79

Area optimization (optimizing DSP48E usage)

I am trying to map, place & route a large design on a Xilinx Virtex 6 FPGA Target Device : xc6vlx550t Target Package :...
1 comments posted 15yrs
posted by vivek.menon79
1 comments posted 15yrs posted by vivek.menon79

Area Optimization

Hi all, I have a design (written in VHDL) targetting the Spartan 6 series, and it's oversubscribed for LUTs. Can anyone...
24 comments posted 15yrs
posted by chead
24 comments posted 15yrs posted by chead

Variable Optimized Away

Hello, I am having a problem where Xilinx ISE is trimming away a variable that I need, tempShifts. I can still implemen...
5 comments posted 15yrs
posted by ballcalvin
5 comments posted 15yrs posted by ballcalvin

multiplication in indexation

Hello everyone I want to do a for loop in order to repeat the same construction and use the number of the loop to creat...
3 comments posted 15yrs
posted by alexis.gabin
3 comments posted 15yrs posted by alexis.gabin

Looking for bitgen Virtex7 and Kintex7 support

Hello, It appears that bitgen in ISE 13.1 supports Virtex7 and Kintex7 implementation up to but not including bitstream...
3 comments posted 15yrs
posted by neil.steiner
3 comments posted 15yrs posted by neil.steiner

verilog task and vhdl

Hi all, I've a functional model of a PHY chip in verilog with a lot of tasks to stimualte change on signals at the inte...
10 comments posted 15yrs
posted by carlo.beccia
10 comments posted 15yrs posted by carlo.beccia