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Random behavior of xilinx simple dual port block ram

Hi, I am using xilinx 12.3 for synthesis and implementation of my design and i am facing 2 problems. I don't know if anyone else has faced them or not.

Problem 1: I am using xilinx simple dual port block ram in my design generated by xilinx 12.3. The problem is its random behavior on reading. Sometimes it gives output 1 clock cycle after the address has been changed.And sometimes it gives output on the same clock when the address is changed. I designed my logic according to the behavior of data coming out after 1 clock cycle of address. And every time the other case happens, my data coming out of RAM becomes invalid. I didn't choose the pipelined output option or anything that could put a flip flop on the output stage. But still data was coming out 1 clock cycle delayed so by watching this behavior i designed my logic, so kindly tell me what to do, maybe there's something i am missing or something i need to know to make it work.

Actually i have 2 RAMs ,byte wide each. The incoming data is 2bytes wide so i write 1 byte to RAM1 and 2nd byte to RAM2. And i read in the same manner i.e. one byte from RAM1 and 2nd byte from RAM2.And i update my read address after i have read the data from RAM2.

Problem 2: I am using xilinx FIFO generated by xilinx 12.3 in my design and i cannot read from it unless i have written at least 8,9 bytes to it. Even if i give it a read signal, it is ignored and empty signal stays high even though i have written some bytes in to it. As soon as 8 bytes have been written, the empty signal goes low and i can read the data then. Is this the proper behavior or am i the only one facing it?

Kindly help me with this thing. Thanks a lot.

Regards

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Reply to
salimbaba
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Problem 1 questions: How did you discover this behavior? Simulation? Chipscope? If chipscope, does it work in functional simulation? If so, can you describe difference between simulation stimulus and chipscope stimulus? Are you using separate clocks to write/read data to/from dpram? Does your design pass static timing analysis for all clock domains? What is the exact relationship between the write cycles and read cycles? Did you use coregen to create the dpram? If so, what latency does it say your dpram will have? It will alter this depending on if you select primitive/core output regs.

Problem 2 questions: Maybe you have unintentionally configured and are using a programmable almost empty flag?

- John

Reply to
jc

Additional questions on Problem 2:

What are the write clock and read clock frequencies? You *do* understand that the empty flag gets synchronized to the read clock?

If you write one word and then wait a long time does the empty flag eventually go low?

Is this behavior noted in simulation or in the real world? If in simulation did you wait at least 100 ns for global set/reset to end before writing the FIFO?

-- Gabor

Reply to
Gabor

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