Best syntheses

You will get a bit better performance with Synplify, but do you really want to have to pay a lot of money for it. Not sure of the current price of Synplify but I think its in the thousands of dollars. I would of thought you would be better off using a faster fpga like Spartan 6.

Jon

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Yes I know the price, I would be in the range of $1-20000 I guess, that is the same as one month of work.

A newer FPGA would be great but not when you have systems all over the planet, that will make Synplicity a bargain if it does the job :)

Have you lately done something with Synplicity and Xilinx 13.1?

/michael

To be honest I think you can probably multiply your Synplify estimate by about x5. Anyway I dont really think you are going to get something like a

50% perfromance increase with Synplify, maybe 10% or 20%. I think that XST has improved a lot and the gap to the other tools isn't as big as it maybe was a few years back. I can't believe that you are getting worst performance by upgrading to to 13.1 from what you had with an older version. What frequency are you tring to achieve and how much is it failing?

Jon

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Who said 13.1 was worse than 9.2, I did not say that!

My question was if you or anyone else have any experience with the latest Xilinx and a third party syntheses tool!

/michael

I misunderstood and thought that you where saying that you had a design in

9.2 which was fine and after moving to 13 you have problems. I guess it depends by how much you are missing timing to if Synplify would help you. Personally I would think it will not make a big improvement over XST.

Jon

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No,I have design and it needs to be improved I and I don't belive in some fantastic tool or miracle which means that I need to try and gain

10-15% here and there in the hope that the result will be the 50-60% I need to make it work.

/michael

Don't expect 50-60% speed improvement from a different synthesis tool! Look at re-architecting the design itself. Identify the slow parts and improve them. If you can add one or more pipeline stages this is relatively easy, but if you can't add a pipeline stage, can you move part of the critical computation to an earlier or later stage?

There are some benefits to be had from floorplanning the speed-critical sections, perhaps explore if PlanAhead can help you meet your targets.

Finally, the next highest speed grade on the chip itself may be worth up to 15%.

- Brian

For sure no, I was hoping that a change of synth would make say 10-15% then I would make it a go.

But, have you used any other synth tools lately?

This is where I expect to gain the remaining 30-40 %, but as I wrote I need to try both a tool change and recoding some parts.

Hmm, I have actually never exlored PlanAhead if that would help. Have you used it?

I already have the fastest and all boards are also already made and in use so that is not an option.

/michael

Mentor Leonardo (years ago!) but not lately. I found my time better spent on improving the design, but YMMV.

Do you have any specific reason for believing the improvement here is so limited?

Not PlanAhead but in the ISE 6.1/7.1 era I played extensively with the earlier Floorplanner, now replaced by PlanAhead. It had serious problems supporting hierarchical and reusable blocks, but...

I could take a block that PARed at 80MHz and get 120MHz out of it with careful floorplanning, and (working around said problems) reuse that block multiple times with PAR placing less critical parts of the design. However, above a certain level of congestion, PAR would route other signals through my carefully floorplanned blocks, destroying some of the additional performance.

Now (1) I can't say how this gain transfers to PlanAhead, and (2) PAR might get closer to optimal performance these days, but it's definitely worth looking into as a source of improvement.

- Brian

It also helps to play with the synthesis and PAR parameters. This is a tedious process because it needs re-running the whole process many times. The defaults most certainly will not get you the best results! Turning on 'optimisation beyond hierarchical blocks' gives a big boost for example.

You don't have to go as far as routing manually. Sometimes the placer puts things like a blockram or multiplier in a bad place (look at the floorplanner). In a few occasions I locked a blockram or multiplier in a fixed position to get a design to meet timing constraints.

--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

l

PlanAhead is well worth a look. It won't affect synthesis results, but it will ensure map/par are used as efficiently as possible. Even without any floorplanning done at all, it can automatically try multiple 'strategies' to get the best performance out of the map/par tools. Floorplanning (for the little amount I had to do to achieve my targets) is easy, and it will also import previous implementations so you can see where your critical path was physically placed, and just floor-plan that bit, and then re-implement. So in that way it can offer quick turn-around with minimal up front work, if just a few paths are giving trouble.

I am qualified to answer your question. I am seeing clock->clock gains in the 3~5% range changing synthesizers. Initial reports show gains larger than that, but those gains shrink when the timing constraints are applied properly.

Brian Drummond

Assuming that webpack supports your device you might do better buying several PCs and creating a linux server farm. Then you can automatically synthesize overnight with many P&R seeds. We do this, but we have 10+ firmware guys sending builds to the farm all the time so its obviously cost effective for us.

Michael,

as others have said, don't expect too much from a third-party synthesis too= l. XST is a really good synthesis tool now, and I'm using it in all of my X= ilinx projects.

There are lots of strategies for improving logic utilization and/or timing,= the most effective usually being optimizations of the RTL code such as red= ucing the number of logic levels, leveraging built-in hard-macros, removing= resets etc.

The best advice I can give you is to show your design to a qualified consul= tant near you. It will cost you some money, but you'll learn a lot and he m= ay catch other issues in the process. Another option is of course to switch= to a device with a faster speed grade.

Hope this helps,

Guy Eschemann

XST is a really good synthesis tool now, and I'm using it in all of my Xilinx projects.

the most effective usually being optimizations of the RTL code such as reducing the number of logic levels, leveraging built-in hard-macros, removing resets etc.

consultant near you. It will cost you some money, but you'll learn a lot and he may catch other issues in the process. Another option is of course to switch to a device with a faster speed grade.

I agree with you, but as the FPGA gets more filled routing tends to be a critical issue in my experience so timing constraints as you wrote is vital.

It is not so easy to find someone that is really good and can pinpoint the weekness in a design in a relative short period of time IMHO.

So as I wrote, if a tool can fix 5-10% then that is very well invested money usually, xst has improved alot and works great but how much has the other vendors(read Synopsys) improved their tools is the question!

xst is catching up but are they ahead or on par with tools like Synopsys?

/michael

tool. XST is a really good synthesis tool now, and I'm using it in all of = my Xilinx projects.

ing, the most effective usually being optimizations of the RTL code such as= reducing the number of logic levels, leveraging built-in hard-macros, remo= ving resets etc.

nsultant near you. It will cost you some money, but you'll learn a lot and = he may catch other issues in the process. Another option is of course to sw= itch to a device with a faster speed grade.

al.

Michael,

I don't have any comparison data between XST and Synplify. However I saw many times, that another synthesis tool can give you 10-15% improvement in timing, or even more, it is very design dependent.

I'd suggest to contact Synopsys/Synplify and ask for a trial. They definitely will give you a ~15 days license to try for free ... and possibly they might be even willing to help (advise how) to get your target timing.

-- Alexy