Hi,
> I need to take out two square wave signals from the Virtex II Pro FPGA
> board(XC2VP30, package ff896) with good signal shape and less jitter
> value. The frequency of the two square wave signals are around 40MHz
> and one is the delayed version of the other. I am trying to evaluate
> the performance of a delay generator block inside the FPGA. Hence, the
> shape and precision of the delays is of greater importance to me. I
> have tried to take the signals through various pins on the board
> including the high speed expansion connector. But I found that only
> when the signals are routed out through the EXT_CLK_P(G15) and
> EXT_CLK_N(F15) pins, the jitter performance is the best. But there is
> a funny thing happening when I observe the two waveforms on a scope.
> Below are the two cases. Looks like, when the signal levels of the two
> signals are different, the signal with ZERO logic goes up to around
> 0.2*Vsupply and at the same time the signal with logic '1' goes down
> by around 0.2Vsupply. Can anybody suggest how can I avoid such a
> situation? I feel there is some sort of resistor coupling between
> these two signals. But, can I =A0disable this coupling by changing some
> setting in the ucf file? This is the entry in the ucf file
> corresponding to the two pins mentioned above.
>
> NET "clk_in_copy" =A0LOC =3D "G15" | IOSTANDARD =3D LVTTL =A0| SLEW =3D F=
AST |
DRIVE =3D 12 ;
> #EXTERNAL_CLOCK_P=3DG15
>
> NET "op_from_delay_chip_copy" =A0LOC =3D "F15" | IOSTANDARD =3D LVTTL | S=
LEW
=3D FAST | DRIVE =3D 12 ;
> #EXTERNAL_CLOCK_N=3DF15
>
> Please suggest a way to set these signals such that the coupling
> between these two signals is nullified and I can use them as two true
> single ended outputs.
>
> Here is an illustration of the case.https://picasaweb.google.com/lh/webUp=load?uname=3Dpratap.iisc&aid=3D56081...
>
> Waiting for some helpful answers.
> Thanks and regards,
> Pratap
Sorry...The link for the picture was wrogly pasted...Here is the correct link.
formatting link