Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15253 Threads Posts
to

Can a glitch-free mux be designed in an FPGA?

Hi: The simplest incarnation of a 2-to-1 multiplexer can be described by the equation: y = ~s & a | s & b where 'y' is...
14 comments posted 15yrs
posted by crobcBOGUS
14 comments posted 15yrs posted by crobcBOGUS

Problem with xilinx 12.3 Timing Analyzer

Hi, I am using xilinx 12.3 for my synthesis and implementation. I am having issues running timing analyzer, the problem...
0 comments posted 15yrs
posted by a1234573
0 comments posted 15yrs posted by a1234573

AVI container and VGA display

hi all! I'm working on the Spartan 3E started with mapping MJPEG decoder. I had the source code of the JPEG deccoding,...
1 comments posted 15yrs
posted by dothetan.040490
1 comments posted 15yrs posted by dothetan.040490

Verify failed between address 0x80000 and 0x8FFFF

Hello, I've been attempting to basically run through the mem_test template and tutorial,on Cyclone® III EP3C120 chip bo...
6 comments posted 15yrs
posted by harishac
6 comments posted 15yrs posted by harishac

Modelsim

Does anyone know if its possible to change the waveform signals so that they are in hex instead of binary. I dont want...
5 comments posted 15yrs
posted by maxascent
5 comments posted 15yrs posted by maxascent

Scoping a glitch

Hi: Today I took scope shots of a clock input to my Xilinx Spartan 3e, Digilent NEXYS2 board. The clock goes to a count...
23 comments posted 15yrs
posted by crobcBOGUS
23 comments posted 15yrs posted by crobcBOGUS

please see me

snipped-for-privacy@rediffmail.com
0 comments posted 15yrs
posted by mveni.nirmala
0 comments posted 15yrs posted by mveni.nirmala

spartan 3a ethernet

for this project, http://www.fpga4fun.com/10BASE-T.html what things need to be changed in order to make it work in spar...
1 comments posted 15yrs
posted by alasli86
1 comments posted 15yrs posted by alasli86

Best syntheses

Hi, I have been using Xilins XST for a while and have come to a performance problem which leads me to think of if there...
16 comments posted 15yrs
posted by michael_laajanen
16 comments posted 15yrs posted by michael_laajanen

DDR SDRAM Configuration problem on XUPV2P

Hi! So, I'm using XUPV2P board (http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,794&Prod=XUPV2P). And I'm...
0 comments posted 15yrs
posted by hrcrnjak
0 comments posted 15yrs posted by hrcrnjak

FPGA cards with memory bus interface

Good day everyone I am fairly new to FPGA based architectures, and I'm interested in applications that are very sensiti...
0 comments posted 15yrs
posted by ka.aly
0 comments posted 15yrs posted by ka.aly