Field-Programmable Gate Arrays

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PowerPC soft-core?

In XCELL issue 52, page 19 Xilinx claims that: V4-PowerPC reduces power 10:1 compared to FPGA Fabric built version (of...
14 comments posted 21yrs
posted by antti
14 comments posted 21yrs posted by antti

Xilinx EDK on Linux

Hi folks, two things about the EDK on Linux: 1) If I have paid for BaseX 6.3i (and received an upgrade to 7.1i), and al...
0 comments posted 21yrs
posted by news
0 comments posted 21yrs posted by news

Power Net Seminar Announcement

I'll be presenting a Net Seminar on both FPGA and HardCopy II power this Thursday, March 11, at 11 am Pacific Standard...
2 comments posted 21yrs
posted by no_spam
2 comments posted 21yrs posted by no_spam

Need help regarding DMA ..

Hi Guys.. I need to write in VHDL code to do a DMA from SDRAM to my IP on the new ML 310 board..I have lot of questions...
0 comments posted 21yrs
posted by beeraka
0 comments posted 21yrs posted by beeraka

OCIDEC3 testbench failure

I've only just started looking at the abovementioned module. I'm attempting to run the testbench as supplied with the O...
3 comments posted 21yrs
posted by markm
3 comments posted 21yrs posted by markm

Block RAM Initialization - RAMB16_S2

hi All, I am trying to initialize the BLOCK RAM :- RAM16_S2 in a design using the following statements On simulation us...
3 comments posted 21yrs
posted by faizal
3 comments posted 21yrs posted by faizal

Free simulator

Hello, I would like to test my implementation of a DSP block (CORDIC-based quadrature mixer + several filters and decim...
4 comments posted 21yrs
posted by wyderskiREMOVE
4 comments posted 21yrs posted by wyderskiREMOVE

WLAN in VHDL

Hi, I am thinking about implementing a WLAN Interface with a FPGA. Has anybody done this before, or does anybody have so...
2 comments posted 21yrs
posted by benjamin
2 comments posted 21yrs posted by benjamin

question about salary

Hello, everyone. I could not find am answer on the web for the following question, which i am not quite comfortable to...
3 comments posted 21yrs
posted by muravinv
3 comments posted 21yrs posted by muravinv

Xilinx ISE 7.1 - Can this get any worse?

I got my ISE 7.1 update DHL'd to me this morning, here is my experience so far A problem... I tried to install 7.1 in t...
22 comments posted 21yrs
posted by andyesquire
22 comments posted 21yrs posted by andyesquire

DDR simulation

I have a problem when simulating with samsung ddr behavioral model, I have tested my design with micron behavioral mode...
2 comments posted 21yrs
posted by ibrahim_magdy_ibrahim
2 comments posted 21yrs posted by ibrahim_magdy_ibrahim

PAL problems (again)

Hello from the Eighth Doctor (Apologies if this question is not group appropriate.) It seems my company's perenial prob...
7 comments posted 21yrs
posted by drwho8__NOTME__
7 comments posted 21yrs posted by drwho8__NOTME__

TPS75003 for FPGAs

Has anyone checked out the new TI power supply for FPGAs, the TPS75003: http://focus.ti.com/docs/prod/folders/print/tps...
4 comments posted 21yrs
posted by wyvwyv
4 comments posted 21yrs posted by wyvwyv

RS 232 receiver using spartan 3 board

I am trying to capture RS232 data on the xilinx spartan 3 fpga on the spartan 3 development board..I have had no luck y...
11 comments posted 21yrs
posted by bhaskarstays
11 comments posted 21yrs posted by bhaskarstays