Field-Programmable Gate Arrays

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Post-map simulation models

Hi everyone... Why is my statemachine not functioning the first many clock-cycles of the post-map simulation? Any explan...
1 comments posted 21yrs
posted by 64bitNOnoNOSPAM
1 comments posted 21yrs posted by 64bitNOnoNOSPAM

DATA2MEM, how do I get the ELF file?

My scheme is like this, I generated a 32Bit*1024word DPRAM with Coregen and inserted that into my design to store some...
2 comments posted 21yrs
posted by lin_mulin
2 comments posted 21yrs posted by lin_mulin

Is the Xilinx EDK free?

I am a hobbyist, actually an embedded software engineer trying to learn about verilog and FPGAs, and would like some ad...
13 comments posted 21yrs
posted by pm940
13 comments posted 21yrs posted by pm940

FPGA and Verilog question

Hello! I am very new to news groups, sorry if I'm doing something wrong. Couldn't you give me some useful links or some...
0 comments posted 21yrs
posted by dfdfdfdf
0 comments posted 21yrs posted by dfdfdfdf

FIR choice

Hi all, I'm implementing a Digital Down Converter for Virtex II pro device. I think I'll not use the builtin DDC IP cor...
8 comments posted 21yrs
posted by nemesis
8 comments posted 21yrs posted by nemesis

Stratix II vs Virtex 4

Hello everyone, I have a rather high performance design that acts as a high through-put data path with some DSP manipul...
3 comments posted 21yrs
posted by e_s_p_i_a_n_
3 comments posted 21yrs posted by e_s_p_i_a_n_

One-hot statemachine design problems

Hi everyone, I try to construct this statemachine as described in VHDL below: (the machine is supposed to set the hold...
9 comments posted 21yrs
posted by 64bitNOnoNOSPAM
9 comments posted 21yrs posted by 64bitNOnoNOSPAM

XC3S50 or EPM1270?

Group, Well, I need to choose between XC3S50 and EPM1270. Both have pros and cons. I list them below, and I'd like to a...
3 comments posted 21yrs
posted by vax9000
3 comments posted 21yrs posted by vax9000

rocketio

Hi, I would like some help from roketio users to find what is the maximum realizable freq we can get out of it. I hear...
14 comments posted 21yrs
posted by res0rsef
14 comments posted 21yrs posted by res0rsef

Avnet Xilinx Virtex-II Pro Development Kit

board : Avnet Xilinx Virtex-II Development Kit fpga : Xilinx Virtex II Pro 20 ==> 2 ppc405, and so on ... problem : avn...
0 comments posted 21yrs
posted by mindroad
0 comments posted 21yrs posted by mindroad

XC4VFX12 price/delivery ?

Has anyone actually purchased an XC4VFX12 yet? They supposedly went on the market in January; parts don't show up in Xi...
1 comments posted 21yrs
posted by ptsmith
1 comments posted 21yrs posted by ptsmith

Spartan 3E vs. Cyclone2

Hi, I'm evaluating low cost FPGA's for a new design starting end next month. Besides XC3S2000, EP1C20 and EC33 (I know,...
24 comments posted 21yrs
posted by lb.edc
24 comments posted 21yrs posted by lb.edc

Xilinx - ucf file parsing errors

The Xilinx memory generator tool generates ucf files that have lines in them such as: NET "ddr1_top0/data_read0/fifo*_w...
1 comments posted 21yrs
posted by sbakke
1 comments posted 21yrs posted by sbakke