Xilinx ISE 7.1 - Can this get any worse?

Hi Andy,

Try out Quartus II. You can download the free version (called "Web Edition") from our website

The Quartus GUI is generally pretty easy-to-use and has the look-and-feel of a modern Windows application.

If you need help understanding the Altera flow, see AN307: Altera Design Flow for Xilinx Users

Also useful is the Xilinx to Altera design migration website

Regards,

Paul Leventis Altera Corp.

When I purchased a development kit for my own projects, the development software played as much a factor in my decision as the target device. What it came down to was, me asking myself, what is going to effect my design more, the device or the design software? No matter what the specs are on the device if the design software had short comings, flaws or limited what I could do with the device, the target device no longer mattered as much.

Searching this group I found users having problems installing and maintaing their development environment. Xilinx tech support seemed to help them find a solution but in the process how do you get back the time that you spent fixing your environment - some of these engineers had spent 1 -3 days fixing their environment.

Going back to something my grandfather taught me, "Don't fix something that isn't broken." In the software world is if you have a working environment and the software vendor comes out with a new release don't upgrade unless there is a feature that you can't live without. Let the people who need the new features get burned by the new releases. Wait 2

-3 months for fixes and services packs come out to fix issues with a new release.

Some of this is just plain common sense but find people today ignore the obvious.

Derek

does it support V II Pro and the likes ? (nope, i don't mean migration;o)

sorry, couldn't resist ;o) l

If you create the device files, it does.

Don't worry I have a sense of humor.

I too dislike the user interfaces of todays leading FPGA providers. I don't think that either A or X have a useful or productive tool.

BUT, what works for me very well, is to understand the flow, and use makefiles and scripts to drive the command line tools. I have been very successful with this method. My development cycle looks like this: 1) create a deign in verilog (including verification); 2) edit ucf file; 3) run my script to create a bit file from my rtl; 4) bring up FPGA.

Once in a blue moon I still start up xps (EDK) to configure an SoC. But I usually just use the tools for the basic build, and than manually edit the appropriate configuration files, and rerun gmake ...

Cheers, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

Your Partner for IP Cores, Design, Verification and Synthesis

Not that I expect any different from the group Altera pusher, but have you ever tried ISE???

I can't believe that even you would even suggest Quartus, it is just as backwards as the ISE interface!

Hi Big,

We'd like to hear your view about how Quartus can be made better for your needs.

- Subroto Datta Altera Corp.

I agree with script based design flow. In fact, once you have tried it, you will never ... ever ... go back to gui. The backend Xilinx flow (ngdbuild ... map .... par .... bitgen) have not changed in years. Individual tool options have obviously to match new architectures.

In a shameless plug of my website, I have a dos based script avaiable for download. It accepts command line two command line options ... name of the base design.edf and the revision number. It uses the revision number as an appendix for final output of filename, and pretty importantly, uses to fill in the user ID as a bitgen option. This is a quick way of scanning a device chain an determining revision levels of on board devices.

Key point though is that these script based approach defines the design flow and synthesis parameters in a way which is absolutely portable and self-documenting, are frees user from the vagaries of GUI releases.

-- Regards, John Retta Owner and Designer Retta Technical Consulting Inc.

A Colorado based Xilinx design consultant.

email : snipped-for-privacy@rtc-inc.com web :

I am still waiting on the latest ISE to show up so I can't comment. I will say that I like the new Quartus software, although I do not use anything but text entry, so most of my work is done in Multiedit for both tools.

Always like the topological display of VHDL modules in other tools like ispLever or Actel's Libero...

It is painful to import a VHDL design into Quartus and manually arrange the file order...

Ah yeah..when is Altera striking with a free Linux version? (o;

rick

Hi Jedi,

Can you expand on this? Haven't got the slightest idea what you mean. I'm envisioning a Mercator projection of desing blocks on a map...

Yep. Dunno whether there's work on this, but you're right, doing a 2-pass parse/compile/elaborate would be handy. Then again, this would mostly make sense when building a project for the first time. Maybe something for the New Project Wizard.

I'm pushing for this as well. Would you be OK with a GUI-less version? (anyone interested raise their hands!). Altera pays royalties on the GUI under Linux and Solaris, so if you can get by without a GUI, Altera can truly ship something free.

Best regards,

Ben

version?

GUI

can

I second that.

I guess marketing puts today a lot of pressure about user appealing IDEs, but if it were up to me I would put all my effort in getting out efficient, heavily tested and well documented shell tools before shipping monolithic, un-intuitive, visually bloated software. It would be nice to have Altera tools for Linux that way, or with a very light but well-thought interface (Synplify comes to my mind).

If licensing is an issue, there are very good cross-platform free GUI tools. I think Lattice is using wxWidgets for their new IDE. Altera and Xilinx already use Eclipse for their CPU SDKs, maybe they should unify all with it (perhaps that is what they are planning to do?).

C'mon, people went to the moon using slide rules, and the first ICs were layout with scissor-cut mylar over kitchen tables. It can't be

*that* hard!

My 2 cents.

-- PabloBleyerKocik / pablo /"Reliable software must kill people reliably." @bleyer.org / -- Andy Mickel

Hi Ben

Oh yes. I can't be the only one here who would much rather run everything from a Makefile.

Many moons ago I went through the agony of reverse engineering how to run XST, map, par, etc. from the commandline (under Wine), but that was ISE and I didn't keep it up.

Cheers, Tommy

If I'd have Altera FPGA, definitely yes. I probably would have considered purchasing Altera, if there would have been decent Linux software out to try. Now it's a bit late, though.

There needs to be an easy tutorial on using the CLI tools, but I trust Altera can do it, or they already have.

I am up and running with 7.1 now. I have not seen Foundation after version 3. I guess it looks alright. I do not plan on using anything but text driven designs so the all of the graphical data entry won't help me. It's going to take me some time to really give good feedback on it.

Maybe something for both Altera and Xilinx. If you are really interested in some feedback, I would personally take the time to enter data into an on-line survey about your tools if you set one up. Just a thought.

I had hopes of going back to Foundation (I need to stop having those) of being able to port some older designs. It seems it is able to read projects from version 4, forward. I have written Xilinx to see if I can get a copy of version 4 to port older designs to it and then to 7. Has anyone tried this for fun?

Hi,

Yes, I have tried ISE -- the OP asked for an alternative. Quartus isn't perfect, but I think the GUI is more intuitive and has a lower learning curve, and the tool is generally more integrated. Or for those script-lovers, you can script up the various pieces of the tool to run without having to ever look at the GUI.

The OP was asking for an alteranative, and I provided one.

Regards,

Paul

No, you're not the only one. I run both Quartus and ISE on Linux with Makefiles (well in the Quartus case most of the work is done in Tcl). I prefer to check all the files out from CVS, run make which will run synthesis, ngdbuild, map, par, bitgen, trce, netgen, and optionally upload the bit file (using impact in batch mode) to the FPGA.

The only FPGA GUI tool I use every now and then is the FPGA editor (I use signalscan for my simulations).

If GUI is Driving Under Influence, then what does GUI mean? Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Hi Tuukka,

There's a whopping big TCL scripting manual in dead-tree format (200+ pages if I'm correct) that comes with Quartus 4.2. Also, work is under way to document each and every setting that can be set in the GUI and that the Quartus TCL interpreter understands.

Then of course there's the quartus_sh --qhelp command that will give you online help for the command-line option of every Quartus command.

Best regards,

Ben

pages

to

the

You can save the trees and read the 358 page document from

The document being referred to by Ben is the Quartus Scripting Reference Manual. It is slight misnomer to call it a Tcl scripting reference. This document covers two different approaches for scripting, each with their own strengths.

One is command line scripting, where you call the different command line executables quartus_map, quartus_fit, quartus_tan, quartus_eda, quartus_asm and quartus_pgm with command line options. If you are familiar with the Xilinx compiler executables with their - switches on the command line this will be very easy to understand.

The second approach allows you to use the Tcl programming language for creating your design flows. This is more powerful than command line scripting as you can use the rich Tcl API supported by the Quartus executables to script and automate your design flows, right from setting up your project, through compilation and verification. For e.g. if you wanted to control our flow based on the condition of certain design objects in your compiler report, or create custom timing analysis reports the Tcl approach is the way to go.

Hope this helps, Subroto Datta Altera Corp.