Am I allowed to change the pin location on the same bank generated b MIG for my virtex4 design ? Would it not be a hassle or restricted i I am forced to use the exact pin location for my DDR2 design ? One o my Virtex4 eval board has it's own fixed DDR2 pins and I would lik MIG to follow those pins constraint. Thanks a lot
anyone able to help me please
Howdy,
I've not used MIG, so I don't know what kind of placement constraint(s) it places on the design, but I find it a little hard to believe that you could only use the set of pins that it chooses. With the exception, of course, that any clock pins (GCLK and CC_LC/BUFIO pins) must move to other clock pins.
Good luck,
Marc
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