Block RAM Initialization - RAMB16_S2

you can create your own ROM block declaring an array of std_logic_vector that is constant, i don't remember well if you should necessary ragister adress_in and data_out but for frequency it's better (name are just for example you could choose what you want)

ex:

entity block_ROM is Port ( clk : in std_logic; adress_in : in std_logic (2 downto 0); data_out : out std_logic_vector(7 downto 0) ) end block_ROM;

architecture Behavioral of block_ROM is

signal adress_reg: std_logic_vector(2 downto 0); signal data_reg : std_logic_vector(7 downto 0);

type TYPE_ROM is array (8 downto 0) of std_logic_vector(7 downto 0);

----------------------------------------------------

constant memory : TYPE_ROM := ( "00000000", "01111000", "01000100", "01111100", "01000010", "01000010", "01111100", "00000000",

);

------------------------------------------------------- begin process(clk) begin if rising_edge(clk) then adress_reg the

This is what I've been using. The low address stuff is on the right end.

INIT_00 : bit_vector(255 downto 0) := -- VIOLET BLUE GREEN ?????? ORANGE RED BROWN TEAL X"0080017000980101000170010070408000015AD0000101A00001608000707001";

Have you looked in the FAQ? Maybe this will help:

=================== Philip Freidin snipped-for-privacy@fpga-faq.org Host for