OCIDEC3 testbench failure

Mar 22, 2005 3 Replies
M

I've only just started looking at the abovementioned module. I'm attempting to run the testbench as supplied with the OCEIDEC3 core, but it fails with...



INFO: WISHBONE MASTER MODEL INSTANTIATED (test.m0) # ***************************************************** # *** IO Test 1 *** # *** Testing WISHBONE wait state insertion, and *** # *** iordy assertion. *** # ***************************************************** # *** MODE SELECT: 'iordy' enable: 0, wb-delay: 0 iordy_del: 0 # >>> Running Read Only test 1 ... (36500) # >>> Running Read/Write test 1 ... (995600) # >>> Running Read/Write test 2 ... (2947600) # >>> Running Read/Write test 3 ... (4899600) # ************************************* # ERROR: Watch Dog Counter Expired



Anyone had experience with this?



Regards, Mark


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M

How is this going to work?

[ata_device.v]

always @(posedge ata_dior) begin dout = mem[ addr ]; dout_en = 1; end

always @(posedge ata_dior) begin dout_en = 0; end

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R

Try to ask in the OpenCores discussion forum. Thats where you downloaded the module from, right ? I know for a fact that the developer of this module does read the OpenCores discussion forum ...

Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

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Your Partner for IP Cores, Design, Verification and Synthesis

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M

And how would you know that? ;)

OK, shall do! Thanks.

Regards, Mark

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