Field-Programmable Gate Arrays

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RLOC question

hello, i am using RLOC statement as .. //synthesis attribute rloc of d1 is X12Y11 As far as i understand, these X-Y co-...
2 comments posted 21yrs
posted by varunjindal
2 comments posted 21yrs posted by varunjindal

MIMO Channel Estimation WCDMA

Hello ALl; Could anyone provide me with useful link about the design of a MIMO system for channel estimation in the upli...
0 comments posted 21yrs
posted by mnamky
0 comments posted 21yrs posted by mnamky

Error synthesizing two Xilinx MacFir core

Hi all, I'm trying to implement a filter switch. I have two different filters (filter30 and filter5, realized with the...
0 comments posted 21yrs
posted by nemesis
0 comments posted 21yrs posted by nemesis

Quartus POWER_UP_LEVEL bug?

I want a FF in my EPM7128S project to be '0' at power-up; be later set by an external input; and never subsequently res...
2 comments posted 21yrs
posted by andrew
2 comments posted 21yrs posted by andrew

General question about soft CPUs

I am looking for some information about how "real" this soft CPU technology is. I'm working with someone who has become...
3 comments posted 21yrs
posted by smkraft
3 comments posted 21yrs posted by smkraft

5V PCI interface

Hi! I'm making a PCI card which currently has the Xilinx Spartan-II designed in beacuse of its ability to interface dir...
14 comments posted 21yrs
posted by sorry
14 comments posted 21yrs posted by sorry

Ethnet samples using EDK??

hello, i am freshly learning using EDK now and i want to try a simple webserver application but i found the doc of EDK...
4 comments posted 21yrs
posted by qx0103
4 comments posted 21yrs posted by qx0103

Global buffer feeding non clock pins in VIRTEX II

In my design (in a Virtex II) there are 2 clocks, each of them on global buffer and feeding 2 sets of distinct register...
5 comments posted 21yrs
posted by giachella.g
5 comments posted 21yrs posted by giachella.g

2 bit multiplier

Hi, I hv tried to run the following 2bit multiplier vhdl code in xilinx... and getting following error... HDLParsers:16...
3 comments posted 21yrs
posted by xiibweb
3 comments posted 21yrs posted by xiibweb

How do I disable Microblaze on-chip hw debug

Hi, I have used the Xilinx XPS to debug a design on a custom board (on-chip hw debug). Now, I want to disable the debug...
9 comments posted 21yrs
posted by nospam.nospam
9 comments posted 21yrs posted by nospam.nospam

Import user Core with a Tri-state Port to EDK

Hello, I'm using Edk 6.3i with service pack 2 and have created a user core, which has a Tri-state Port with import/crea...
1 comments posted 21yrs
posted by khezerloo
1 comments posted 21yrs posted by khezerloo

question using xapp333

Dear all, I would like to make use of the XAPP333 vhdl codes provided by Xilinx on my Spartan 2E. It's an I2C bus contr...
1 comments posted 21yrs
posted by greenplanet
1 comments posted 21yrs posted by greenplanet

Xilinx VirtexII master serial mode problem(cclk)

I have a custom board using Xilinx VirtexII. i'm using a master-serial mode. After power on reset(Power status is good)...
8 comments posted 21yrs
posted by false0
8 comments posted 21yrs posted by false0