I have a custom board using Xilinx VirtexII. i'm using a master-serial mode. After power on reset(Power status is good) cclk must output clock. But clock just logic high. I can't find why clock is not out! Thanks to read my poor English message.
"eou4" schrieb im Newsbeitrag news: snipped-for-privacy@l41g2000cwc.googlegroups.com...
check M0 M1 M2, INIT_B, PROG_B and powersupplies if all of the above are correct then the CCLK should start
antti
M0 M1 M2 is tied with pull-up resistors. INIT_B is connected with XC18(xilinx PROM)'s OE/reset pin. (pull-up with 4.7k) PROG_B is connected with XC18's /CF pin. (pull-up with 4.7k) Power(VCCINT, VCCAUX, VCCO,GND) levels are good, and mode setting correct. But cclk isn't start..
M0 M1 M2 is tied with pull-up resistors. INIT_B is connected with XC18(xilinx PROM)'s OE/reset pin. (pull-up with 4.7k) PROG_B is connected with XC18's /CF pin. (pull-up with 4.7k) Power(VCCINT, VCCAUX, VCCO,GND) levels are good, and mode setting correct. But cclk isn't start..
M0 M1 M2 is tied with pull-up resistors. INIT_B is connected with XC18(xilinx PROM)'s OE/reset pin. (pull-up with 4.7k) PROG_B is connected with XC18's /CF pin. (pull-up with 4.7k) Power(VCCINT, VCCAUX, VCCO,GND) levels are good, and mode setting correct. But cclk isn't start..
M0 M1 M2 correct("000"). Power levels are correct. INIT_B, PROG_B are logic high. These pins are connected with 4.7k pull-up and xilinx PROM(OE, /CF)
I usually think of "up" as being a 1. If you really have pullups, that's probably your problem.
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Oh, my mistake.. It Connected pull-down resistors. No pull-up resistors.
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