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General question about soft CPUs

I am looking for some information about how "real" this soft CPU technology is. I'm working with someone who has become enamored with the "soft CPU" concept from the FPGA vendors. I have a number of what seem to me to be "gotta know" questions about this technology, and I don't know how to get them answered. There are big picture questions like:

- What are the compelling reasons to go this route?

- If we take this path, can it be made to *really* work, i.e. never fail from one in a billion type errors?

- How much longer will it take to do it this way compared to the "old" way of using a separate processor and FPGA?

Then I have small picture questions like:

- If you need to add peripherals (like UARTs, PWM contoller, etc., etc.) how well does this work?

- Is the whole development environment reasonable?

I looked around on the web, and there sure is a lot of marketing material, especially from Xilinx and Altera, but that's not what I'm looking for. Do you know anywhere I could get a description of how a real commercial project has gone for somebody, so that I can get some of my questions answered?

Thanks! Steve

Reply to
Steve
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Hi Steve,

The Nios Community Forum can provide you answers to your question on the Nios II, Nios processors, their associated development environment, tool chain support, RTOS's and peripherals from Altera Corp. You can access it at

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Hope this helps.

Subroto Datta Altera Corp.

Steve wrote:

what

"old"

Reply to
Subroto Datta

what

As real as anything else one might want to put into an FPGA.

There are some reasons that drive this, depending on developer though

Control, previuosly I used ARM7TDMI external, as the FPGA got more capability & did more work, the system was stuck with same external cpu that was starting to become a bottleneck. Soft core cpus allow for the EE to get control of the system and insert cpu power where it's needed rather than depending on the ASIC supplier to help out. The worlds greatest cpu isn't much use on the ouitside if you want it inside for fine grain control. Some cpus are so tiny (PicoBlaze) they are hardly recognizeable to a manager, but they may be perfectly fine for doing some odd job FSMs. More interesting soft cpus may be just as capable as many external cpus (

Reply to
JJ

That depends very much on your product, market, and definition process. There are both advantages and disadvantages in SoftCPU.

+You can roll almost anything that marketing dreams up [if you can keep up with their changes :) ] +Systems that need high bandwidth, sepecialised peripheral coupling can work very well in soft-cpu +SoftCPUs cover a very wide range: Some of the tiny ones, can run from block ram, and can be very good INIT and handshake problem solvers.

-You will quite often need "next size" FPGA to include the CPU. [The FPGA vendors love this feature.. ]

-It is not actually a single chip solution : You need the loader PROM, and some form of code execution memory. That can mean wide.high speed data busses, and many EMC issues. It is also not trivial to select and source that execution memory. Again, you can "next size" the FPGA, to get enough Block Ram to run all code on chip.

-Power consumption can take quite a hit. Static Icc on newest FPGAs is terrible, when compared with Std Microcontrollers.

You can, of course, have more than one controller in a design.

You might use a small uC for WDOG, Init, ADC, BrownOut, and power save tasks, and a larger SoftCPU, or choose one of the new larger FLASH uC, and load the (now smaller) FPGA from that.

For uC FPGA interface you can choose parallel, or the newer faster serial interfaces.

This is what I'd call mature technology. Field reliability is another area in itself...

Very well, if the peripheral mix is outside the typical uC. If you want 64 PWM channels, or special serials etc.

Just don't try and add ADCs as peripherals, or 32KHz clock oscillators, or Brownout detectors..... :)

-jg

Reply to
Jim Granville

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