2 bit multiplier

Apr 12, 2005 3 Replies
X

Hi,



I hv tried to run the following 2bit multiplier vhdl code in xilinx... and getting following error...



HDLParsers:164 - "C:/Projects/knm/2bit.vhd" Line 11. parse error, unexpected INTEGER_LITERAL, expecting IDENTIFIER



I am just a beginner any1 kindly help....



thnx



John



here is the code...


**********************************************************

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;


---- Uncomment the following library declaration if instantiating



---- any Xilinx primitives in this code.



--library UNISIM;



--use UNISIM.VComponents.all;



entity 2bit is Port ( A0 : in std_logic_vector(1 downto 0); A1 : in std_logic_vector(1 downto 0); B0 : in std_logic_vector(1 downto 0); B1 : in std_logic_vector(1 downto 0); B2 : in std_logic_vector(3 downto 0); C0 : out std_logic_vector(3 downto 0); C1 : out std_logic_vector(3 downto 0); C2 : out std_logic_vector(3 downto 0); C3 : out std_logic_vector(3 downto 0)); end 2bit;



architecture Behavioral of 2bit is



begin C0


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E

xilinx...

Your Entity and file name is "2bit".

I GUESS the problem is first character '2'.

Try alphabet at first.

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M

From

formatting link
/ pacman. 2 bit x 2 bit mul element.

4 inputs fit into one LUT, so you can use a case statement to make it easier to read without a performance hit. This should take 4 luts total. There are much better ways to do bigger multipliers, search this group as it has been discussed many times.

Cheers, Mike.

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity PACMAN_MUL_PARTIAL is port ( A : in std_logic_vector(1 downto 0); B : in std_logic_vector(1 downto 0); R : out std_logic_vector(3 downto 0) ); end;

architecture RTL of PACMAN_MUL_PARTIAL is

begin p_lut_comb : process(A,B) variable ip : std_logic_vector(3 downto 0); begin ip := A & B; case ip is when "0000" => r r r r r r r r r r r r r r r r null; end case; end process; end architecture RTL;

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