Quartus POWER_UP_LEVEL bug?

I want a FF in my EPM7128S project to be '0' at power-up; be later set by an external input; and never subsequently reset. I placed an SRFF with S to the external input; clock to the clock; and R to ground. I assumed it would power-up at '0' but I got analysis and synthesis errors:

"Info: Power-up level of register inst is not specified -- using unspecified power-up level"

and "output pins are stuck at VCC or GND" - so I created an assignment:

set_instance_assignment -name POWER_UP_LEVEL LOW -to inst

I was surprised it needed this, but it seems to work. That sorted, I placed an inverter between the Q output of the SRFF and an external output pin - I want the FF to drive an external active-low signal. This doesn't work in the simulator or the real silicon: the output is permanently asserted. But, if I connect another output directly to q - so I have both q and /q output pins - then it works!

I'm guessing that Quartus can't invert the signal between the macrocell FF and output pin, so it needs to use another macrocell just for the inverter, but something goes wrong with the optimisation. Am I warm? Is this a known bug? Is there some option I need to set, or must I dedicate an output pin for the unwanted true q - just to make the /q output work??

I'm using Quartus II 4.1 Web Edition.

You can download a Quartus archive of this from

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Try it first as-is, then delete the true output and re-run the simulation.


Reply to
Andrew Holme
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Andrew can you send me your email so that an engineer can contact you on this. Thanks for the test case and we are working on it.

Subroto Datta Altera Corp.

Reply to
Subroto Datta


My e-mail is here

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Reply to
Andrew Holme

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