Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15254 Threads Posts
to

Worth reading in Field-Programmable Gate Arrays

process trouble, error: multi source

Hi, I want to set the load input for a counter to 1 and set it at the next clk automatically back to 0. But I get this...
2 comments posted 21yrs
posted by benjamin
2 comments posted 21yrs posted by benjamin

PLB IPIF on Virtex 2 Pro

I encountered the following problem in a design of a reprogrammable processing device. Not to go into to much detail :...
0 comments posted 21yrs
posted by mindroad
0 comments posted 21yrs posted by mindroad

xilinx virtex 4 download cable

Hi i have buy, virtex 4 evalutation board. In the box there isn't any cable for the bitstream download. Can i download...
15 comments posted 21yrs
posted by opb
15 comments posted 21yrs posted by opb

State of MAX7000S I/O pins before programming

In the MAX7000S datasheet, it says the I/O pins are tri-stated and (weakly) pulled-up, to avoid board conflicts, during...
10 comments posted 21yrs
posted by andrew
10 comments posted 21yrs posted by andrew

lcd controller - how to realize it?

Hi, I want to write an interface in vhdl for a HD44780 LCD Controller. What is the best methodology to do that? Moore-A...
6 comments posted 21yrs
posted by benjamin
6 comments posted 21yrs posted by benjamin

Timing

Hi, I have an A/D-converter attached to my Spartan3 starter kit, running at 100Mhz Maximum speed. But the A/D converter...
9 comments posted 21yrs
posted by 64bitNOnoSPAMno
9 comments posted 21yrs posted by 64bitNOnoSPAMno

DC component removal in FPGA

Hello, I am designing a system using Virtex 4 FPGA. The FPGA is interfaced with a 12-bit A/D. The problem is that the A...
9 comments posted 21yrs
posted by saurster
9 comments posted 21yrs posted by saurster

Application using coprocessor interface

Hi Folks, Can anyone point to or give me examples of applications that have been known to use the coprocessor interface...
1 comments posted 21yrs
posted by pk4
1 comments posted 21yrs posted by pk4

free HDL ebook?

Hi, are there any free books on HDLs (verilog preferred) online? I found several "getting started" tutorials, but what...
0 comments posted 21yrs
posted by annonce05_nospam
0 comments posted 21yrs posted by annonce05_nospam

Xilinx Platform Studio - Vertex II Pro board

Hai all, I have a virtex pro II fpga board. I would be thankful if anyone can tell me how can we generate bit streams f...
1 comments posted 21yrs
posted by nkishorebabu123
1 comments posted 21yrs posted by nkishorebabu123

Altera and VHDL library

Hi, with the latest quartus II software I created two VHDL packages. After testing the packages I wanted to combine the...
6 comments posted 21yrs
posted by haribeau
6 comments posted 21yrs posted by haribeau

CCD and Graphics - which FPGA?

Hi all, some years have gone since I did something with FPGAs and I am aware that technology has moved forward signific...
7 comments posted 21yrs
posted by die_les_ich_nicht
7 comments posted 21yrs posted by die_les_ich_nicht

easyfpga is not easy

hi, I have brought a cyclone development board (EZ1CUSB-12) from easyfpga (www.easyfpga.com) . The CDROM version is 0.9...
3 comments posted 21yrs
posted by ypuilee
3 comments posted 21yrs posted by ypuilee

xapp134 on sdram controllers: @ bits reordering?

In this design, and in others I've seen around, the bank bits are MSB. What would you think about reordering address bi...
1 comments posted 21yrs
posted by robertp
1 comments posted 21yrs posted by robertp