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Global buffer feeding non clock pins in VIRTEX II

In my design (in a Virtex II) there are 2 clocks, each of them on global buffer and feeding 2 sets of distinct registers (block A and block B). The clocks then feed a clock switching circuit (not a BUFGMUX) and the resulting clock feeds another part of the design (block C). From PAR report I get

WARNING:CLK Net:FPGA_CLK_BUFGP may have excessive skew because 1 NON-CLK pins failed to route using a CLK template.

WARNING:CLK Net:SMP_CK_MASTER_TO_CPU may have excessive skew because 1 NON-CLK pins failed to route using a CLK template.

I suppose this message warns about a potentially unacceptable skew between blocks A/B and block C , but the skew inside block A or block B is still guaranteed to be low.

Am I right ? Thanks

Reply to
g. giachella
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Howdy,

Depending on how you are getting signals between blocks A/B and C, there is the potential for trouble - but the MUCH bigger problem is that you will have unacceptable skew *within* block C. Unless you floorplan the flops within block C (and do so VERY intelligently), you're asking for trouble. Even if you do the muxing with LUTs, send the output of the LUT to a global clock.

And yes, the skew within blocks A and B should be fine.

Marc

Reply to
Marc Randolph

Would he be able to apply some timing constraints to the flops in block C and maybe the clock to block C to guarantee that the clock skew is acceptable.

gja

Reply to
gja

[this is in regards to using local routing for the clk in block C]

In theory, yes. In practice, the number of flops that the tools can route to with similar prop delay (aka low-skew) is limited. Wild guess: a couple hundred FF's might be reachable. Maybe more, maybe less. And it would not be surprising to me if most or all of them needed to be hand placed.

Marc

Reply to
Marc Randolph

Could you clarify this point ? Why shouldn't the skew inside block C be low, assuming it is also an a global clock line ?

Thanks

Reply to
g. giachella

It's not on a global clock line if it's the output of a LUT, that's why he said send the output of the LUT to a global clock buf.

Reply to
gja

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