Latest threads in Field-Programmable Gate Arrays

Add on bus

Looking to see if anyone out there has verilog or vhdl code that implements the "add on bus." Couldn't find any on openc...

0 21yrs

themarenas

0 21yrs themarenas

Virtex4 running at 360Mhz DDR

I'm about to use Virtex 4, and wonder if this is achievable. All literature seems to indicate that it is, but I'd like...

40 21yrs

fastgreen2000

40 21yrs fastgreen2000

dividing the clcok by 2.5

Hello Guys, I have to divide an clock by 2.5. I cannot use the DCM of virtex 2 pro has my clock is 10 MHZ which is too...

4 21yrs

stud_lang_jap

4 21yrs stud_lang_jap

PCI PCIX LoGi Core Problem

Hello All, I am using Xilinx PCI/PCIX Logicore. FPGA is configured with a default bitstream first (either PCI or PCIX)...

0 21yrs

kedarpapte

0 21yrs kedarpapte

CAM implementation on Lattice EC

Hi, I want to do the following: 32-Word CAM, 10-Bit Wide With Altera Cyclone or Stratix it can be done just by using am...

0 21yrs

ALuPin

0 21yrs ALuPin

Clock speed problem. How can I proceed?

I have a 500K gate, 40MHz design. When I first implemented that for xc2v6000, P&R succeeded with 2ns margin. Now I deci...

0 21yrs

invalicd

0 21yrs invalicd

Configuring an XC3S400 Spartan 3 with JTAG

Hello, I want to configure a Spartan 3 with an ARM controller comporting several GPIO pins (0-3,3v), from which I use 4...

6 21yrs

jerome.maye

6 21yrs jerome.maye

DDR speed of the XUPV2P Board from Digilent

Hi, I am doing stuff with Displays. The data rate is about 3 gigabits/s for the pixels. I am thinking about using the X...

15 21yrs

benjamin

15 21yrs benjamin

Altera Quartus Timing Models

How do I perform a timing analysis using Quartus, with a worst case temperature of less than the default for the device...

4 21yrs

alanmyler

4 21yrs alanmyler

dcm's for increasing clock speed

when can dcm's be used (xilinx ise) to improve clock speed of a given design? suppose my design synthesizes at 75mhz bu...

3 21yrs

wallge

3 21yrs wallge

Altera: Maxplus rules!

I have a Maxplus design which is a year or more old which was compiled with Maxplus. So far so good. I am required to m...

9 21yrs

Fred

9 21yrs Fred

TRACE and Modelsim Timing Help

Dear Gurus, I hope that someone would help me on how to interpret the following timing parameters. Thank You very much...

3 21yrs

galiero

3 21yrs galiero

Uart16550 can't receive data over 16byte a time

I send 50 bytes character to serial port of UART1655 in FPGA Board,But only the first 16 bytes of received data is corr...

10 21yrs

mlpei279

10 21yrs mlpei279

Quartus II - multicyle option

Hi, I setup the multcyle constraint for a reg-to-reg path as : set_instance_assignment -name MULTICYCLE 2 -from "dlatch...

1 21yrs

laurent.gauch

1 21yrs laurent.gauch

Xilinx VIIPro mixed configuration voltages

I'm using a VIIPro with Bank 4 Vcco set to 3.3V. The PROM is an XCF04S which has separate Vccint (must be 3.3V), Vccjta...

2 21yrs

enquiries

2 21yrs enquiries

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