CAM implementation on Lattice EC

Hi,

I want to do the following:

With Altera Cyclone or Stratix it can be done just by using am RAM:2-Port template. That leads to the following component:

data[0] wraddress[14..0] wren rdaddress[9..0] rden clock q[31..0]

rdaddress[9..0] corresponds to the 10bit-word to search (within one clock cycle) and q[31..0] shows the position of the hit.

If there is more than one hit I perform a second stage search with a different module. data[0] is kept HIGH to write data into the CAM, it is kept LOW when erasing the CAM entry.

So my question: Is such a CAM implementation possible for Lattice EC FPGAs ?

Or is the architecture of the integrated RAM blocks quite different so that it will not work ?

The Lattice IP MANAGER has the following pseudo dual port memory module:

WrClock WrClockEn WE RdClock RdClockEn WrAddress Data Rdaddress Q

Do "WrClockEn" and "RdClockEn" correspond to the "wren" and "rden" in Cyclone devices? Why does Lattice have an additional "WE" but no additional "RE" ?

Thank you for your opinions.

Rgds Andr=E9