Field-Programmable Gate Arrays

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Xilinx VIIPro mixed configuration voltages

I'm using a VIIPro with Bank 4 Vcco set to 3.3V. The PROM is an XCF04S which has separate Vccint (must be 3.3V), Vccjta...
2 comments posted 21yrs
posted by enquiries
2 comments posted 21yrs posted by enquiries

8051 IP core

hi all... i would like to know wether anyone of you has used Oregano's free 8051 IP core. Also i read somewhere that th...
16 comments posted 21yrs
posted by Puneetsingh81
16 comments posted 21yrs posted by Puneetsingh81

true dual port memory v/s simple dual port memory

Hi all, I wanted to know the differnce between a true dual port memory and a simple dual port memory in FPGA context. Th...
10 comments posted 21yrs
posted by praveen.kantharajapura
10 comments posted 21yrs posted by praveen.kantharajapura

how to add library

Hi all, I would like to add the library: libm.a into my project, but I don't know how. who knows? Please help me. Thank...
0 comments posted 21yrs
posted by lnzhao
0 comments posted 21yrs posted by lnzhao

Max7000ae and GCLRn

Hi, I have troubles with my reset using Altera MAX7000AE. Can I re-route the GCLR signal (global signal) from an intern...
1 comments posted 21yrs
posted by laurent.gauch
1 comments posted 21yrs posted by laurent.gauch

Flagging XST to suppress the warning

Hi folks, Let's say I have a module with 2 inputs and 2 outputs module1(input1, input2, output1, output2) Then I instan...
1 comments posted 21yrs
posted by u1000393
1 comments posted 21yrs posted by u1000393

EDK: user logic on opb bus in microblaze system

Hi, I have a microblaze system with uart,intc and a user ip on the opb bus.I have used the create new peripheral proced...
1 comments posted 21yrs
posted by kittyawake
1 comments posted 21yrs posted by kittyawake

Looking for Xilinx Power-PC consultant

Hello, An Israeli company is looking for a consultant to help our Software and Hardware team to develop embedded proces...
2 comments posted 21yrs
posted by ppc_consultant
2 comments posted 21yrs posted by ppc_consultant

Fake Buffers in ECS

Hi Folks, I'm using ECS (yes, I know...). Now, ECS forces one to insert a buffer whenever one wants to rename a bus. I...
2 comments posted 21yrs
posted by knittel
2 comments posted 21yrs posted by knittel

float computing: how to add libm.a

I want to do float computing with xilinx FPGA, but I don't know how.In order to add libm.a into the project, I know tha...
1 comments posted 21yrs
posted by lnzhao
1 comments posted 21yrs posted by lnzhao

Clock delay vs. clock skew

What is the correct definition of clock delay or clock skew? And what is the difference between those two things! Thanks...
5 comments posted 21yrs
posted by 64bitNOnospamNO
5 comments posted 21yrs posted by 64bitNOnospamNO

IP core supply

plz touch me more detail if u need the following ip. brahms snipped-for-privacy@yahoo.it ******************************...
7 comments posted 21yrs
posted by brahms_view
7 comments posted 21yrs posted by brahms_view