Hello Guys, I have to divide an clock by 2.5. I cannot use the DCM of virtex 2 pro has my clock is 10 MHZ which is too less for the DCM to handle. I think this division can be done using state machine (posedge and negedge).....but i cannot figure out on what state should i derive the clock and how many state are required??
Can any one please provide suggestions
thanks and regards williams
Philip Freidin Fliptronics
Philip Freidin wrote: :
From which the following reference is particularly relevant, as it includes a divide-by-2.5 circuit:
Richard.
Untrue. Use the DCM to multiply by 4 using the CLKFX mode. The minimum CLKIN is 1MHz in this case, CLKFX output still has a minimum of 24MHz but that's OK as you've now got 40MHz. Divide that by 10. Cheers, Syms.
"The multiply by 4 in the DCM, divide by 10 in the fabric" has the advantage that it is insensitive to the incoming 10 MHz duty cycle. And you can even get a perfect 50% output duty cycle if you do the divide-by-10 the right way around.
Peter Alfke, Xilinx Applications
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