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2.5/3.3 LVPECL in Virtex

Not another how-to question. I got app notes and opinions coming out my ears already.

I was just wondering if it was impossible to have maintained the 3.3V LVDS and LVPECL stuff for another couple of generations. The 3.3V LVPECL is still pretty much widely used. On Semi, for example, is only now getting some of 2.5V stuff out there. Some only say 2.5V online and there's no mention of it in the data sheet when you download it.

My problem is trying to design new plug-in cards to existing units with

3.3V LVPECL. I'd like to use Virtex4 chixps because they are far cheaper right now than the Virtex-2 chips. For eample, Avnet quotes $3K on the LX100 and $9K on the 2V8000!

I've also got situations where the data rates are such that I'm Real Unhappy putting a resistor network into the path, especially since I have a connector already involved in the impedance discontinuity landscape.

So I was just wondering: is my current grief for a greater good? ;-)

Reply to
Quiet Desperation
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PECL is bad because the outputs aren't matched to the line. Check one of your wax smeared app notes and look at the output structure. LVDS and now, (even better), CML outputs fix that and can run much faster with better SI. That's why things are changing, and OnSemi and Micrel are making some great parts. As for no more HowTo, you might wanna stop reading now! The Xilinx differential inputs have enormous common mode range, I'd be surprised if you couldn't make that work somehow. Agreed you might need to AC couple the outputs if you're afraid of resistors. ;-) Check out this (yet another app note) to fix the DC!

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Remember, if it was easy, anyone could do it, and we'd all be paid peanuts! Cheers, Syms.

Reply to
Symon

A partial help is that some of the newer Xilinx families will support input LVDS/ LVPECL on Vccio = 3.3V. Spartan-3 does, V2-Pro does but I am not sure on V4 but probably yes. The general line on outputs is that these need 2.5V but it might be worth investigating what the limitation is.

Here is a useful supporting link

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Another way to tackle this is to run the FPGA with a Vccio = 2.5V and keep the signal swing from your 3.3V devices under the protection diode conduction point of the FPGA I/O i.e. about 3.1V (Vccio = 2.5V exactly). You may be able to run your 3.3V logic at 3.0V to keep the swings in this range or use bus switches to limit swing. Timing penalty is about 250 pS maximum for the bus switches. We do this for 5V/3.3V PCI interfacing in our Broaddown2 and MINI-CAN products and the solution is not necessarily large or costly. There are three 20 bit bus switches on both these products and you can see them on the board pictures on our website next to the PCI edge connector.

John Adair Enterpoint Ltd. - Home of Broaddown2 and MINI-CAN FPGA Development Boards.

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Reply to
John Adair

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