I'm about to use Virtex 4, and wonder if this is achievable. All literature seems to indicate that it is, but I'd like hear what others think and perhaps point out where I need to be careful in the design.
I'd be receiving an LVDS clock pair @ 360Mhz, running part of the internal logic at 360. This internal logic includes DSP48 slices (but need to be pipelined in the fabric since I need more than 48-bit 'C' input for adder). Preliminary testing indicates that it can go above
360 with light user intervention. One thing I'm cautious about is, the rest of logic runs much slower, at 90Mhz. Initially was thinking of using /4 version, but Peter Alfke's post regarding added skews due to loading differences in DCM outputs is making me think about it carefully.For otuput, I'd be using ODDR to multiplex 360 Mhz logic, to send the data out at 360Mhz DDR (so the data can look like 360Mhz 'clock'). Data is LVDS, so is the forwarded LVDS clock pair @ 360Mhz. The receiving device will use both edges of the forwarded 360 Mhz clock to sample the data. Clock to output delay is not good, 3+ ns, but since the clock will be forwarded and will incur effectively the same delay as data (other than IOB-IOB clk skew), as long as I send out 180 deg version of internal 360 clock using ODDR, it should be ok. Not sure what kind of SI issue there will be, however.
I have an option of running it at 180Mhz if 360 is risky. External device will be different. Am I playing too safe by going to 180? Will
360 be a challenge?I'd appreciate feedback.