Hi,
I setup the multcyle constraint for a reg-to-reg path as : set_instance_assignment -name MULTICYCLE 2 -from "dlatch_bus:I12|D[4]"
-to "dlatch_bus:I18|Q[8]"
Also, I setup the global clk frequency as : set_global_assignment -name FMAX_REQUIREMENT "100.0 MHz"
After synth. and P&R with Quartus-II, I still received the warning as:
-> -6.400 ns 60.98 MHz ( period = 16.400 ns ) dlatch_bus:I12|Q[4] dlatch_bus:I18|Q[8] INCLK INCLK 10.000 ns 7.600 ns 14.000 ns
DO YOU HOW TO SETUP CORRECTLY A MULTICYCLE PATH IN QUARTUS II ?
PS: I did the same with Xilinx ISE, and works fine !
Larry,
formatting link