dcm's for increasing clock speed

when can dcm's be used (xilinx ise) to improve clock speed of a given design? suppose my design synthesizes at 75mhz but i need my design to run at 150mhz what can i do to improve performance will dcm's work? better pipelining?

any suggestions appreciated...


Geoffrey Wall
Masters Student in Electrical/Computer Engineering
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geoffrey wall
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The DCM can be used to change a clock frequency, not to alter the synthesized speed of your design. If your synthesizer suggests 75 MHz is the best you can do even though you asked it for 150MHz, chances are your place & route will give you something much closer to 75 MHz operation than

150. Use the synthesis tools or - if they don't give good detail - the place & route tools to tell you what your critical paths are. It may be that you have one congested part of your design that needs better pipelining or a slightly different approach. If the number of paths failing timing are huge and mostly unrelated, you need to use a much faster speed grade part or lower your expectations.

The DCM can be used as a clock doubler with input frequencies of 25 MHz or better. It can also be used in frequency synthesis mode with an input as low as 1 MHz.

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Geoffrey, the DCM just changes the clock frequency. It does not shorten the delays in your design. If you are limited to 75 MHz, there must be some strange excessively long ( >12 ns) delays. Analyze your design, and see where these delays originate. Pipelining is a good way to improve the max clock rate. Once your design CAN run at 150 MHz, then it's time to double the clock frequency, not before. Peter Alfke

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Peter Alfke





I think you are getting confused with the fact that a DCM can improve your I/O timing (but not frequency). By using a DCM you can phase shift to help meet Tco/Tsu requirements. As stated before, DCMs cannot increase max clock rate. If you don't know where to start, get a timing report and look at your critical paths. How many elements are in the path? Is your delay mostly IC delay or routing delay? If it is IC delay, you need to do some pipelining or redesign. If it is routing delay, you need to do some floorplanning.


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John M

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