Field-Programmable Gate Arrays

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Q)BRAM VHDL simulation in modelsim

Hi I have a problem in simulating a memory block (VHDL-written control unit and BlockRAM for Virtex II). BRAM is instan...
2 comments posted 21yrs
posted by pasacco
2 comments posted 21yrs posted by pasacco

how can i save my received data into the SDRAM?

I have receive large character data from RS232, i want to save it in the SDRAM memory, i find the SDRAM is 8M*32, but t...
5 comments posted 21yrs
posted by mlpei279
5 comments posted 21yrs posted by mlpei279

Xilinx "Free ISE WebPACK 7.1i" under Fedora core 3 ?

Hi, Does this "Free ISE WebPACK 7.1i" for linux work with any distribution other than Red Hat Enterprise Linux 3 ? I tr...
9 comments posted 21yrs
posted by georgevarughese
9 comments posted 21yrs posted by georgevarughese

Update Picoblaze Code in Bitstream

Hello, in my actual design im using a few picoblazes. Now I wonder if it is possible to update the code in the bitstrea...
7 comments posted 21yrs
posted by michaeldre
7 comments posted 21yrs posted by michaeldre

V4 vs. Stratix-II...

I'm upgrading a design, and I'm in the early phases of choosing a vendor. I'm trying to compare parts based on experien...
22 comments posted 21yrs
posted by jhallen
22 comments posted 21yrs posted by jhallen

EDK 7.1 with xilinx ML401 ref design

Hi I am wondering again and again if xilinx does any testing of the software they release both ISE 7.1 and EDK 7.1 have...
1 comments posted 21yrs
posted by antti
1 comments posted 21yrs posted by antti

"Mine is bigger than yours..."

It's again time for the annual bragging frenzy, where every FPGA manufacturer claims to have the biggest. It seems so s...
24 comments posted 21yrs
posted by peter
24 comments posted 21yrs posted by peter

Re: Counting Clocks

in your code, the value of synch_found is never reset after it has found the first synchronisation byte... Ben >I have...
1 comments posted 21yrs
posted by benjamin.toddREMOVEALLCAPITALS
1 comments posted 21yrs posted by benjamin.toddREMOVEALLCAPITALS

initializing fifo pointers to simulate overflow

Hi Folks, I am using Altera's LPM FIFOs. These are deep fifos and was wondering if there are any techniques that people...
5 comments posted 21yrs
posted by fpgabuilder-news
5 comments posted 21yrs posted by fpgabuilder-news

High radix multiplier

Hello everybody, I would like to implement a multiplier with word size equal to 16. However I read some book, for examp...
3 comments posted 21yrs
posted by 5218invalid
3 comments posted 21yrs posted by 5218invalid

Auto-select clock for virtual pins

Hi, I have constrained some pins in my top-level design as virtual pins: (Altera QuartusII v. 4.2 SP1 To Assignment Nam...
8 comments posted 21yrs
posted by ALuPin
8 comments posted 21yrs posted by ALuPin

Input Maximum Delay timing assignment in Altera

Hi, in the Quartus Help I have found the following: #Input Delay from Pin to Input Register logic option # #A logic opt...
4 comments posted 21yrs
posted by ALuPin
4 comments posted 21yrs posted by ALuPin

EDK 7.1 XMD and platform USB cable

Hi does anyone have had full success using the xilinx platform USB Cable and XMD in EKD 7.1? I was trying to check out...
1 comments posted 21yrs
posted by antti
1 comments posted 21yrs posted by antti