How to turn off auto bufg insertion in ISE 7.1 ???

In older versions the ECS schematic would not insert these, but for HDL you would attach a BUFFER_TYPE attribute to the net. Check out the constraints guide to see how.

Yes, with ISE 6.x one would add a BUFG(x) symbol to explicitly insert a bufg in the schematic. I want to avoid placing an attribute BUFFER_TYPE=none on a LOT of nets that XST thinks should be a clock net; If that's even possible since it's not listed as a constraint under schematic flow. Anyone know of a global way to turn off auto bufg insertion?