Update Picoblaze Code in Bitstream

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Check out Ken Chapmans reply to this in the PicoBlaze forum:

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Darn... the link is broken...

Here's the post:

Ken Chapman - 03:54am Dec 14, 2004 PST (#1 of 1) Reply

A new version of DATA2MEM is in development and will support the update of the

Please contact me directly ( snipped-for-privacy@xilinx.com) if you would like to help me verify it further.

Thanks to the Xilinx Software Development team for adding support of BRAM in this aspect ratio.

Regards,

Ken

Hello,

Here it works, thanks for your help

Michael

Michael,

As of ISE 7.1 Data2MEM does support 18-bit datawidths.

You need to add a BMM and MEM file to the top level of your ISE project.

The BMM should have syntax to describe the instantiation of the BlockRAM you instantiated. An example BMM file is:

//////////////////////////////////////////////////////////////////////// ADDRESS_SPACE picoblaze1 RAMB18 INDEX_ADDRESSING [0x00000000:0x000003FF] BUS_BLOCK top/picoblaze1/myram [17:0]; END_BUS_BLOCK; END_ADDRESS_SPACE; ////////////////////////////////////////////////////////////////////////

In the above BMM file example the name 'picoblaze1' could be anything. Further the label 'top/picoblaze1/myram' is the instantiation name of the blockRAM with complete hierarchy. To obtain the instantiation name of the blockRAM you could run the tools one and then open up FPGA Editor to see the complete instantiation name of the blockRAM.

The second file you have to add to the Project Navigator project is a MEM file. A MEM file is essentially a HEX file (output from KCPSM assembler) with '@0' as the first line. Currently, you must create the MEM file by hand from the HEX file.

Every time the time stamp of the MEM file changes then the 'Generate Bitstream' task becomes unchecked in Project Navigator. All you have to do is is Run 'Generate Bitsteam' and the a bitstream will be generated with the updated values without running through Synthesis/Translate/MAP/PAR.

Cheers, Shal> Hello,

The following may be of interest to you (full-text PDF available from the link):

Programmable Parallel Coprocessor Architectures for Reconfigurable System-on-Chip.

Williams, John A. and Bergmann, Neil W. (2004)

We propose a hybrid rSoC parallel processing architecture consisting of a central 32-bit RISC microprocessor interconnected to an array of 8-bit microcontrollers as coprocessing nodes. The central processor runs an embedded Linux operating system, with the coprocessor nodes mapped into a virtual file system, by which they can be controlled and reprogrammed. The hardware and software architectures are detailed, and several useful application contexts are proposed. Supporting theoretical analysis is also presented.

Regards,

John

Impressive. Did you look at data links between the PicoBlaze units ? - that would further off-load the main CPU, and ease situations where a single task proved too much for one Picoblaze ?

-jg

No I didn't, however PicoBlaze interfacing is so simple that adding either direct-wired or buffered (FIFO) links between multiple Picos should be pretty straight forward.

We since have expanded the concepts in that paper to multi-microblaze systems - their native FSL interfaces make it trivial to connect them up to each other in arbitrary topologies, and also makes it easy to drop a bit of custom hardware in place of a CPU if you decide you need more performance or smaller logic utilisation.

BTW, the device driver developed for that work is in the public uClinux source tree, it's a generic uClinux driver for FSL peripherals. So, you can interact with pretty much any FSL core from within uClinux, using intuitive open/read/write system calls, just like any other file/device.

Regards,

John