Auto-select clock for virtual pins

Hi Andre,

Virtual pins essentially turn into registers in the current implementation, and hence require a clock for (at least most) timing constraints and the associated timing analysis. The message below is harmless. It is telling you that you didn't assign a clock to the Virtual Pin via the "Virtual Pin Clock" assignment, and that Quartus can't find a reasonable clock to use as a default clock for this Virtual Pin. Quartus searches the fan-in and fan-out cone of the Virtual Pin to see if there's a clock the Virtual Pin feeds or is fed by -- if it finds one, that becomes the default clock for this Virtual Pin. In this case it couldn't find a clock, so this Virtual Pin presumably feeds / is fed by combinational logic only. The code simply gnds the clock.

If you don't care about timing analysis of paths starting or ending on these virtual pins, you don't have to do anything.

If you do care about their timing analysis, you can use the "Virtual Pin Clock" assignment to specify what clock domain you want them to be part of. Or, you can simply specify a "Maximum Delay" timing constraint to or from these virtual pins, if that's easier and matches what you want.

Hope this helps,

Vaughn Altera [v b e t z (at) altera.com]

I have constrained some pins in my top-level design as virtual pins: (Altera QuartusII v. 4.2 SP1

To Assignment Name Value Enabled Pin_name Virtual Pin On Yes ...

After fitting I get the following warning message for all constrained output pins:

Warning : Can't fit auto-select clock for virtual pins "Pin_name1"

-- setting clock to GND Warning : Can't fit auto-select clock for virtual pins "Pin_name2"

-- setting clock to GND ...

When looking at the Quartus Help it is said under ACTION : Assign the Virtual Clock Pin logic option to an appropriate clock signal in the design.

But I have not chosen a Virtual CLOCK Pin assignment but Virtual Pins !!! So why do I get these warnings ?

Rgds André

Hi Vaughn,

Pin

part of.

from

thank you for your answer.

Where in the Assignment Editor (which column)do I assign the Virtual Pin Clock for the Virtual Pins ?

Rgds Andr=E9

Answered last question by myself.

I have made the virtual clock pin assignment in the Assignment Editor.

To Assignment name Value Enabled

clk_90_sys Virtual Pin Clock clk_90_sys Yes

And yet when compiling the design I get the warnings described in my first post.

The problem is that I NEED the virtual pins to be registered and therefore clocked because I want to have a look at them with SignalTapII. Or is that a problem because of using virtual pins ?

Rgds Andr=E9

Andre,

The syntax of the assignment you made looks wrong to me. You want to set a "virtual pin clock" on some "virtual pin", say Pin_name1 (name from your original post). The syntax for that is:

To Assignment name Value Enabled

Pin_name1 Virtual Pin Clock clk_90_sys Yes

Note that I changed the "To" value to the name of the virtual pin. The assignment above says "make virtual pin Pin_name1 use signal clk_90_sys as its clock.

Hope this helps.

Vaughn [v b e t z (at) altera.com]

I have made the virtual clock pin assignment in the Assignment Editor.

To Assignment name Value Enabled

clk_90_sys Virtual Pin Clock clk_90_sys Yes

And yet when compiling the design I get the warnings described in my first post.

The problem is that I NEED the virtual pins to be registered and therefore clocked because I want to have a look at them with SignalTapII. Or is that a problem because of using virtual pins ?

Rgds André

I have tried the following:

To Assignment Name Value Enabled

Pin_name1 Virtual Pin On Yes Pin_name1 Virtual Pin Clock clk_90_sys Yes

clk_90_sys is the clock net name of the clock coming out of the Cyclone PLL. This clock is not routet to IOs, it is an internal clock.

And yet I get the warning: #WARNING: Virtual pin clock "CLK_90_SYS" for virtual pin "Pin_name1" does not exist in the design - auto-selecting clock

In the HELP of Quartus I read the following: CAUSE: You assigned the Virtual Pin Clock logic option to the specified pin. However this pin does not exist in the current design. When this condition occurs, Analysis & Synthesis automatically selects an appropriate virtual pin clock. ACTION: No action is required. To avoid receiving this message in the future, assign the Virtual Pin Clock assignment to an existing clock signal in the design.

But "clk_90_sys" DOES exist. So what I am still doing wrong?

Interesting thing: Some virtual pins do get an external clock coming into the FPGA. For these pins I do not get any warnings.

Best regards Andr=E9

Hi Andre,

The clock name doesn't look correct to me in this assignment. Remember you have to use the clock node (net) name, not the name you gave the timing constraints assigned to the clock (clock settings). You have to specify the full name of the clock net, which will be long when this comes out of a PLL.

Probably the easiest way to get the name of the clock signal is to use the node finder from Assignment Editor. Click on the "To" box of the Virtual Pin Clock assignment. Click on the arrow on the right side. Bring up the node finder, and look for a name something like "pll1|alt_pll|clk0" except longer. That's the name you want.

To Assignment Name Value Enabled

Pin_name1 Virtual Pin On Yes Pin_name1 Virtual Pin Clock ****** Yes

Regards,

Vaughn Altera [v b e t z (at) altera.com]

To Assignment Name Value Enabled

Pin_name1 Virtual Pin On Yes Pin_name1 Virtual Pin Clock clk_90_sys Yes

clk_90_sys is the clock net name of the clock coming out of the Cyclone PLL. This clock is not routet to IOs, it is an internal clock.

And yet I get the warning: #WARNING: Virtual pin clock "CLK_90_SYS" for virtual pin "Pin_name1" does not exist in the design - auto-selecting clock

In the HELP of Quartus I read the following: CAUSE: You assigned the Virtual Pin Clock logic option to the specified pin. However this pin does not exist in the current design. When this condition occurs, Analysis & Synthesis automatically selects an appropriate virtual pin clock. ACTION: No action is required. To avoid receiving this message in the future, assign the Virtual Pin Clock assignment to an existing clock signal in the design.

But "clk_90_sys" DOES exist. So what I am still doing wrong?

Interesting thing: Some virtual pins do get an external clock coming into the FPGA. For these pins I do not get any warnings.

Best regards André

Hi Vaughn,

I have inserted the name of the clock coming out of the PLL

pll_bank3:PLL_B_3|altpll:altpll_component|_clk1

I do not get the warning anymore.

But the strange thing is that I connect the output of the PLL in my top level file to a net with the name "clk_90_sys" So pll_bank3:PLL_B_3|altpll:altpll_component|_clk1 =3D clk_90_sys

And yet it makes a difference, why?

Rgds Andr=E9

Andre,

Quartus only has one name per net. So the long name above is the name of the clock coming out of the PLL.

It sounds like you connected this net to an FPGA output I/O, with a name of clk_90_sys. In that case, the signal going to the board will be called clk_90_sys. However, that signal (clk_90_sys) is driven by an output I/O cell, and is considered a different net than the PLL clock above, which was an input to that I/O cell.

In an ASCII schematic you have:

------------ net = pll_bank3...|_clk1 -------------- net = clk_90_sys PLL block |----------------+------------->| I/O cell |------------------------>

------------ | -------------- | +----> to clock ports of registers

Regards, Vaughn Altera [v b e t z (at) altera.com]