EDK 7.1 with xilinx ML401 ref design


I am wondering again and again if xilinx does any testing of the software they release both ISE 7.1 and EDK 7.1 have service paks already so I assume some bug tesing and FIXIN has been done?

well I am having some trouble with microblaze system that shoud connect to 4

64 bit SDRAM banks using 4 instances of opb2plb bridge.

so, problem, oh well lets take a xilinx own KNOWN WORKING DESIGN and lets see what is done there, so I load the ML401 reference design in EDK 7.1, then I open add edit cores, and hit 'generate address map'



... and XPS is gone!!!

yes it just silently closes itself.

I am having some warnings when doing address generate so I wanted to compare those warning with the warnings that come with xilinx own design, but I can as the xilinx own desing makes xilinx own software to terminate itself.

its not so impossible to test for software bugs, why xilinx isnt doing that? testing with its own design (like the ML401 ref design) would be good test for beta test of new releases. but it has not been done.


Reply to
Antti Lukats
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I agree, im also very frustrated about the general quality of the EDK product.. I wasnt able to synthesize the reference design for the ml401 either.

Reply to
Peter Sørensen

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