Past: I did a lot of leading edge (in terms of size) FPGA designs for ASIC prototyping. Size, usability, and cycle-time is of the essense. In the past, I have used Orca (1996), Virtex , VirtexE, and V2. About
5 years ago, I looked at Altera and Quartus pretty much shot them in the foot.
Current: In the new design, I once again evaluated state of the art FPGAs. For this cycle Virtex4's timeline was a little too late (by a couple of months), so I started in StratixII (2S130s and 2S180s). So far, I have been very impressed with the tools and results.
Note: Altera's FPGA is not totally symmetric. Different types of memory, different type of PLLs, only certain PLLs can do feedback, vertical I/Os are different than horizontal I/Os. I thought this would be difficult to keep straight. However, I am getting to realize the design I am working on is very not symmetric, so this has not been a problem.
Memory: I first thought that having to worry about the different types of memory (512, 4K, 512K) was going to cause a accounting nightmare, but you can actually set it to decide for you. Quartus decides for itself which one to use. I really like this.
Synthesis: I have been impressed with the synthesis results. Not as good as Synplify Pro, but it comes with Quartus II. We are having a problem where Synplify is not finishing on one of the FPGAs and having the Quartus synthesis engine saved us. Also, synthesis in Quartus takes about 2x-3x more computer time than synthesis in Synplify.
Physical Synthesis: I was incredibly impressed with this since it is a check box (vs. psuedo-floorplanning with Amplify or hand modification with Precision). For me, it is the difference between closing and not closing timing. One note though, some of my design grow by 20% when I turn this on, so make sure you have a lot of head room.
Logic: I really like the ALM. It does cut down on the number of levels the logic has to go through. This helps with timing. Despite what either Altera or Xilinx have to say, I really don't need a 1:1 ratio of logic elements to FF. About 10:1 ratio for ASIC prototyping is a better ratio. I would really like to see what other designers see. I would really like to see future families have at least 2x more logic vs. FFs.
PLLs: I like the analog PLLs vs. DPLLs of Xilinx. One warning, if you set QuartusII to decide the PLL type, you may not get to use all the ratios. Kind of bizarre, but that is the way I interpreted the tool. I just set to only use Enhanced and the problem went away.
General: The tool flow is a little bit cleaner, but the Xilinx tool flow was pretty good, so that is a wash. I am not a tcl expert, so it takes a little getting used to. I do like when you finally get all the tcl scripts right, you don't have to remember any switches, but once again a wash.
Support: I am getting great support both locally and from the factory. Of course your mileage will vary and may ultimately determine your choice and your success.
Not used: I did not use processors, high speed transceivers, other IOs.
Cons 1: I was playing around with some different partition and I had a design that was 85% full (in terms of logic) and Quartus II could no route it at all (with no timing constraints). To be fair, I have other partitions with more than 90% that did route. In previous Xilinx devices in the Virtex* family, I only had problems closing time (i.e. routing did not fail) at 95%, so budget your size appropriately.
Cons 2: Currently, there is no flash part that could program more than
1 of these large devices. It really makes the JTAG chain on the board needlessly complicated.
-Edwin