Peter, Austin, someone Xilinxy, can anyone possibly put this in hands where it'll do some good? The cost of updating online PDF documentation is really pretty trivial.
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To whom it may concern:
Page 53 of the Spartan-3 Starter Kit User's Guide claims that:
The A1 expansion connector shares connections with the 256Kx16 SRAM devices, specifically the SRAM address lines, and the OE# and WE# control signals. Similarly, the JTAG chain is available on pins 36 through 40. Pin 20 is the FPGA DOUT/BUSY configuration signal and toggles during the FPGA configuration process.
This, while accurate, is not the entire case. The A1 connector also shares connection with 8 of the SRAM data lines, though this is not indicated in any way by Table 13-2. This information, in fact, can only be deduced by close examination of the schematics, or alternatively when PACE informs you that the pins to your SRAM and the pins making hard connections to the board you've already spun are on the same pin of the FPGA. Had this information been made clear in the user's guide, rather than left out of the explicit statement of connection, I would now be saved a good deal of fairly extensive blue-wiring trying to save this project.
Please update the User's Guide as soon as possible regarding this point, in the interests of saving a future customer my current aggravation.
Regards, Rob Gaddi