Input Maximum Delay timing assignment in Altera

Hi André,

The title talks about "Input max delay", while the help description cited is that for a delay chain setting: "Input delay from pin to input register".

The two are different, and guide the Quartus tool in a different manner. "Input max delay" is a timing constraint, while the "Input delay from pin to input register"other one is a fitter setting to overwrite an delay chain in the I/O.

Quartus is very good at automatically selecting the best delay, so there is really no need to use the "Input delay from pin to input register". Instead, you can use either the "Input max delay / input min delay" or "tsu/th" timing constraint to specify your requirements, and Quartus will do a good job at selecting the best settings (in a timing driven way).

Hope this helps.

Subroto Datta Altera Corp.

in the Quartus Help I have found the following:

#Input Delay from Pin to Input Register logic option # #A logic option that specifies the propagation delay from an input pin #to the data input of the input register implemented in the I/O cell #associated with the pin. This is an advanced option that should be #used only after you have compiled a project, checked the I/O timing, #and determined that the timing is unsatisfactory. For detailed #information on how to use this option, refer to the data sheet for #the device family. # #This option is useful for fine-tuning a design's I/O timing and meet #tSU/tH requirements. # #Legal integer values range from 0 through 63. # #This option is ignored if it is applied to anything other than an #input or bidirectional pin. This option can be set in the Assignment #Editor (Assignments menu). This option is available for CycloneT II #and Stratix® II devices.

So it seems that this feature is not available for Cyclone devices? Is there some alternative method for Cyclone?

Rgds André

Where can I find this assignment type "Input max delay / input min delay" in the Assignment Editor?

Rgds Andr=E9

Subroto Datta schrieb:

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Click on the Assignment Editor->Timing button which is in the upper right corner. This will show only timing related assignment names in the Assignment Name field in the table below. You will have to fill in the From and To fields and the value needed.

You can also use the All button in the upper right corner of the Assignment Editor to obtain a list of every Assignment Name possible which will include these Timing Assignment names also.

Hope this helps.

- Subroto Datta Altera Corp.

Rgds André

Here is some more detail and information on the Input Max Delay/Min Delay for the benefit of other readers of this newsgroup:

You can just type "In" and you will see the Assignment Editor quickly show all assignments that start with "In". The second one in the drop down should be "Input Maximum Delay" and third is "Input Minimum Delay". You need to enter both a "From" and "To" node, where "From" represents your clock reference and the "To" represents the input pin name. Both fields accept wildcards and/or timegroups

If you want to go directly to the QSF file, you can enter:

set_instance_assignment -from -to -name INPUT_MAX_DELAY

set_instance_assignment -from -to -name INPUT_MIN_DELAY

Or if you use Tcl scripting, type

set_input_delay -max/-min -clk_ref -to

in the Quartus Tcl console (View->Utility Windows->Tcl Console) or in the quartus_sh Tcl prompt. quartus_sh is lauched from the command line or DOS box. Make sure that the quartus\bin is on your path where quartus quartus represents the path to the Quartus Installation directory.

For more on the Tcl command, use "quartus_sh --qhelp" and look at the "project" Tcl package.

Output Delays

-------------------

Also note you can do the same for output pins, and use "Output Maximum/Minimum Delay" (Tcl: set_output_delay) instead of "Tco/Min Tco" requirements.

What do these delays represent

---------------------------------------

If you have an ASIC background, you will recognize this type of constraints as most EDA tools use them. They represent the external delay on your board. A simplistic way to see this is that "Input Max/Min Delay" represents the "Tco/Min Tco" of the chip feeding the FPGA plus the board delay, while "Output Max/Min Delay" represents the "Tsu/Th" of the chip fed by the FPGA plus the board delay. These assignments tell the Quartus II Timing Analyzer to basically consider the pins as registers and do simple register to register analysis. This means that you can use Multicycle, Clock Uncertainty, and other features on your I/O paths.

If you want to use this methodology and you have PLLs, you may want to consider upgrading to V5.0. In this release, we introduce "Clock Latency" and for PLLs, we automatically create this clock latency based on the PLL's compensation delay. The advantage of using Clock Latency is that you avoid having to define Multicycle assignments in some cases, so it is a lot easier to use. You have to enable the feature from the "Timing Settings" Dialog box. Click on the "More Settings" and then turn on "Enable Clock Latency" (Tcl/Qsf: "set_global_assignment -name ENABLE_CLOCK_LATENCY ON").

For more on these features, search for "input_max_delay", "output_max_delay" or "clock latency".

Hope this helps,

Subroto Datta

Altera Corp.