Q)BRAM VHDL simulation in modelsim


I have a problem in simulating a memory block (VHDL-written control unit and BlockRAM for Virtex II). BRAM is instantiated as shown below. The problem for me is that the VHDL description of BRAM is not available. The question is that

- Can we simulate it in modelsim SE 6.0c?

- In case only the BRAM-instantiation is enough to simulate and synthesize, is it meaning that simulator/synthesis tool(XST) has the library?

Thankyou in advance for comment

--------------------------------------------------------- . . . component RAMB16_S9 port ( DI : in STD_LOGIC_VECTOR (7 downto 0); DIP : in STD_LOGIC_VECTOR (0 downto 0); EN : in STD_ULOGIC; WE : in STD_ULOGIC; SSR : in STD_ULOGIC; CLK : in STD_ULOGIC; ADDR : in STD_LOGIC_VECTOR (10 downto 0); DO : out STD_LOGIC_VECTOR (7 downto 0); DOP : out STD_LOGIC_VECTOR (0 downto 0)); end component; . . .

-- 1st RAMB16_S9 port map(WE=>we, EN=>en, DIP=>dip, SSR=>ssr, CLK=>clk, ADDR=>addr, DI=>din(7 downto 0), DO=>dout(7 downto 0));

-- 2nd RAMB16_S9 port map(WE=>we, EN=>en, DIP=>dip, SSR=>ssr, CLK=>clk, ADDR=>addr, DI=>din(15 downto 8), DO=>dout(15 downto 8));


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simulation of Xilinx blockram is no problem. You only need the Xilinx unisim library for this (\Xilinx\vhdl\src\unisims\ ) => You must compile this library with modelsim and include to your project.

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it works

thankyou very much for comment

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