Field-Programmable Gate Arrays

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How to use XMD debugger

Hi all, I am using Virtex-II Pro50 to do some experiments. I would like to use XMD to debug, but I couldn't set the bre...
1 comments posted 21yrs
posted by lnzhao
1 comments posted 21yrs posted by lnzhao

Minimum circuit to get Spartan-3 running

Greetings, I have one of the Digilent spartan-3 starter boards, and have been browsing this newsgroup for a while. I th...
5 comments posted 21yrs
posted by nospam
5 comments posted 21yrs posted by nospam

Slice Virtex II = Equivalent gates ??

Hi, I'm interested in knowing how many equivalent gates are included in a VirteX II slice for ASIC development. Thanks.
6 comments posted 21yrs
posted by rarteaga
6 comments posted 21yrs posted by rarteaga

Analog to Digital Converted (ADC) & Spartan 3

Greetings, I am looking at an application that will provide an analog input signal in the 125 to 500 KHz frequency rang...
4 comments posted 21yrs
posted by oth3ll0
4 comments posted 21yrs posted by oth3ll0

how to use libm.a and libc.a

I want to add libc.a and libm.a into my project and use the the standand C functions such as doing float computing, mal...
1 comments posted 21yrs
posted by lnzhao
1 comments posted 21yrs posted by lnzhao

Frequency limitations?

Hi Everyone, I tried to run the processor as well as the OCM with 100/100, 300/100, 300/300 as well as 300/150 MHz comb...
1 comments posted 21yrs
posted by johnsons
1 comments posted 21yrs posted by johnsons

FPGA/Embedded Design Training

Heyas, I've recently graduated college (< 2 years) and in that time have taken up a job which does not do nearly as muc...
2 comments posted 21yrs
posted by kevin
2 comments posted 21yrs posted by kevin

Test the code on FPGA Board...

Hi , I have a Virtex II Pro FPGA Board and I have a verilog HDL code, I synthesized and generated bit stream to configu...
2 comments posted 21yrs
posted by nkishorebabu123
2 comments posted 21yrs posted by nkishorebabu123

strange Microblaze error

Hi, I get the following error, I am not sure how to fix that. I have tried increasing the memory size, but that doesnt...
1 comments posted 21yrs
posted by grabherp23
1 comments posted 21yrs posted by grabherp23

An FPGA eval board at $49!!

Hi gang, Future electronics is offering Altera Cyclone/Nios-II Evaluation Kit for $49. What do other have to say about t...
8 comments posted 21yrs
posted by zingafriend
8 comments posted 21yrs posted by zingafriend

ACTEL design problems

Hi, my ACTEL FPGA design shows significant problems. A bit that is feed in a FIFO will set more than one flipflop. The...
0 comments posted 21yrs
posted by rupert.glaser
0 comments posted 21yrs posted by rupert.glaser

2.5/3.3 LVPECL in Virtex

Not another how-to question. I got app notes and opinions coming out my ears already. I was just wondering if it was im...
2 comments posted 21yrs
posted by nospam
2 comments posted 21yrs posted by nospam