I'm upgrading a design, and I'm in the early phases of choosing a vendor. I'm trying to compare parts based on experience I've had in the past, so I'm focusing on block RAM clock to out delay as a critical performance number:
Altera M4K vs. Xilinx Block RAM clock to out delay, non-registered outputs:
Stratix-II -3 2.46 ns Stratix-II -4 2.828 ns Stratix-II -5 3.393 ns
Xilinx-V4 -11 1.83 ns Xilinx-V4 -10 2.10 ns
Xilinx-V2 -4 2.65 ns (current part)
V4 appears to be 1.62 times faster for the slowest speed grade parts (which I'm probably most interested in, though I should really compare equal priced parts), and slower even than the original V2 design. Am I missing something? Several posts here suggest that Stratix-II interconnect is faster- is there any datasheet evidence to back this up? Lets say the RAM output is at least feeding a 2:1 MUX before being registered, and porbably has to travel ~1/3 the width of the chip.
Also, help me fill in my chart:
Xilinx-V2 -4 439ps Xilinx-V4 -10 200ps Xilinx-V4 -11 170ps Stratix-II ? (can't find any data)
Xilinx-V2 -4 106ps Xilinx-V4 -10 90 ps Xilinx-V4 -11 80 ps Stratix-II ? (can't find any data)
I can do this with fpga_editor in Xilinx. How to do it for Stratix-II ?