Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

[Q] Synthesis : HowTo Preserve FSM encodings

Hi all, I just wonder if there is a possibility to add a constraint on the RTL level (VHDL/Verilog) to make shure that...
3 comments posted 21yrs
posted by meng.engineering
3 comments posted 21yrs posted by meng.engineering

Problem with quartus 5.0 sp1

Hello I've got problem with Quartus 5.0 with Service Pack 1. Problem occurs in compilati'Internal Error: Sub-system: AS...
4 comments posted 21yrs
posted by czebaka
4 comments posted 21yrs posted by czebaka

Modelsim on a remote display

Hallo, I'm using modelsim se into a windows xp pc. There is a way to use it into another windows xp pc with remote deskt...
7 comments posted 21yrs
posted by marcotoschi
7 comments posted 21yrs posted by marcotoschi

Xilinx ISE on remtoe Display

Hi All, I'm trying to persuade xilinx ISE to display on a remote machine. ISE is installed on a solaris box, and I want...
8 comments posted 21yrs
posted by ajg112
8 comments posted 21yrs posted by ajg112

Chipscope pro : timing constraint?

dear chip scope pro users Problem with VIO occurred in ChipScope Pro, ISE6.3. i am (still -: ) exercising VIO,IlA with...
9 comments posted 21yrs
posted by pasacco
9 comments posted 21yrs posted by pasacco

Easy USB2.0 hi-speed device solutions ?

I'm looking for an easy-to-use USB2.0 hi-speed device solution with the minimum of software work required to get a lot...
3 comments posted 21yrs
posted by mike
3 comments posted 21yrs posted by mike

FPGA-Based system design project

Hi friends I am new to this forum...and found that you guys are really helpful t each other with strong knowledge on FP...
3 comments posted 21yrs
posted by chanhanmate260
3 comments posted 21yrs posted by chanhanmate260

Changing data into mapped register

Hallo, I have made a small system based on microblaze. I have made a opb peripheral with register support to transfer d...
0 comments posted 21yrs
posted by marcotoschi
0 comments posted 21yrs posted by marcotoschi

Evolutionary VHDL code example

Hello everyone Does anyone where I can find a simple VHDl code example based on evolutionary algorithms.I am doing a pr...
6 comments posted 21yrs
posted by apsolar
6 comments posted 21yrs posted by apsolar

Antti's last comp.arch.fpga posting

Hi all I am regret to inform you all that this the last time I either post or reply to comp.arch.fpga newsgroup. This d...
9 comments posted 21yrs
posted by antti
9 comments posted 21yrs posted by antti

Altera NIOSII IDE problem???

Hi, Enviroment Board : Nios development kit(cyclone edition)version 3.1 Quartus : version 4.2 NIOSII IDE : version 1.1....
3 comments posted 21yrs
posted by monica_dsz
3 comments posted 21yrs posted by monica_dsz

image sensor

Hi does anybody have a design example of an image sensor connected to programmable logic with HDL code? I want to try t...
5 comments posted 21yrs
posted by bob
5 comments posted 21yrs posted by bob

GSPx 2005 Conference

Hi All, I have just found out about the GSPx 2005 conference and workshop to be held in Santa Clara. Has any one been t...
0 comments posted 21yrs
posted by Sudhir.Singh
0 comments posted 21yrs posted by Sudhir.Singh

XC5200 tool help needed

I am assisting in the debug of a board with XC5202 parts. The design is done using Aldec schematics in the M1.4 environ...
3 comments posted 21yrs
posted by urbpublic
3 comments posted 21yrs posted by urbpublic

Clock generation

Dear everybody, I'm a beginner in using VHDL to build hardware blocks. So, I would like to submit you a problem about c...
4 comments posted 21yrs
posted by alessandro.strazzero
4 comments posted 21yrs posted by alessandro.strazzero