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[Q] Synthesis : HowTo Preserve FSM encodings

Hi all,

I just wonder if there is a possibility to add a constraint on the RTL level (VHDL/Verilog) to make shure that a specific state machine encoding for a particular module/entity is not changed/optimized?

Is this possible, if for the overall design the synthesis tool is given the freedom to do at is best, and therefore maybe re-arrange state vector encoding.

I'am interested for the tools XST from Xilinx, but also others from Synplicity, Mentor etc.

Best Regards Markus

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Reply to
Markus Meng
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sure thats should be possible. there is something called as a dont_touch attribute which you should look for.

Reply to
Neo

It is possible. Check the constrain documentation. In XILINX the constrain called (if i am not mistaken) something like FSM_coding or similar.

--
Alex
Reply to
Alex

for simplify use attribyte SYN_ENUM_ENCODING and SYN_ENCODING = "original" and don't forget to disable FSM Compiler

Reply to
des00

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