Hi all,
I just wonder if there is a possibility to add a constraint on the RTL level (VHDL/Verilog) to make shure that a specific state machine encoding for a particular module/entity is not changed/optimized?
Is this possible, if for the overall design the synthesis tool is given the freedom to do at is best, and therefore maybe re-arrange state vector encoding.
I'am interested for the tools XST from Xilinx, but also others from Synplicity, Mentor etc.
Best Regards Markus
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