Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15255 Threads Posts
to

Worth reading in Field-Programmable Gate Arrays

AHDL Abandoned in Quartus?

Hello, last year there was a post concerning Altera abandoning AHDL in their new tools, such as Quartus. The post also...
4 comments posted 21yrs
posted by jjlindula
4 comments posted 21yrs posted by jjlindula

18-bit ROM in verilog

Hi group I'm trying to infer an 18-bit rom to be put in a block RAM. I'm using a case statement and a clocked address a...
2 comments posted 21yrs
posted by brian.pedersen
2 comments posted 21yrs posted by brian.pedersen

How to disconnect a signal?

Hallo, I have made a small opb peripheral with registers support. Into a state machine I connect slv_reg0 to an externa...
2 comments posted 21yrs
posted by marcotoschi
2 comments posted 21yrs posted by marcotoschi

Spartan-3 configuration -- peculiar problem

Hello All, I'm three days into this configuration problem, so I think it's time to consult the experts. Problem's like...
19 comments posted 21yrs
posted by ScreamingFPGA
19 comments posted 21yrs posted by ScreamingFPGA

VHDL Array indexing Issue in Modelsim

To all, I'm trying to create a test bench where an array data type of "std_logic_vector" is read within a for loop and...
4 comments posted 21yrs
posted by pinod01
4 comments posted 21yrs posted by pinod01

Delay implementation and logic optimization.

Hi guys. Implementing asynchronous delays in my design via a chain of buffer elements (I know it's a bad practise, but...
4 comments posted 21yrs
posted by al.lopich
4 comments posted 21yrs posted by al.lopich

Clock for serializer with a Spartan3

Which is the preferred way to generate the output clock for a deserializer made with a shift register? For example, let...
5 comments posted 21yrs
posted by antonio12358
5 comments posted 21yrs posted by antonio12358

Modular design flow

Hello all, I am currently using xilinx modular design flow to develop a simple design. The top level design has an inou...
3 comments posted 21yrs
posted by FPGA05
3 comments posted 21yrs posted by FPGA05

Avnet spartan3E development board

hi, im hoping to buy the following FPGA development board from Avnet. If anyone got any experiance with it please let m...
3 comments posted 21yrs
posted by manusha
3 comments posted 21yrs posted by manusha

Glitches in Output of FSM

Hi All, I have a state machine which produces control signals (synchronous Reset and Enable) for a synchronous counter....
2 comments posted 21yrs
posted by Sudhir.Singh
2 comments posted 21yrs posted by Sudhir.Singh

Creating EDIF from VHDL

Hey! SUpposing im using Xilinx ISE 4.2, how do I go about creating an EDIF file to load into this as thats the only thi...
3 comments posted 21yrs
posted by 311f037
3 comments posted 21yrs posted by 311f037

Peter Alfke's SPDT Switch Debouncer

Hello Peter, I have a small code snippet: U_IBUF_Key1: IBUF port map(I => InKey1, O => Key1); U_OBUF_Key1: OBUF_S_2 por...
18 comments posted 21yrs
posted by v_mirgorodsky
18 comments posted 21yrs posted by v_mirgorodsky

EDK IPIF + User Core

I am simulating a IPIF + user core using the BFM simulation model and in my test I can succesfully write to the WFIFO (...
1 comments posted 21yrs
posted by nrivera.eng
1 comments posted 21yrs posted by nrivera.eng