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Clock generation

Dear everybody,

I'm a beginner in using VHDL to build hardware blocks. So, I would like to submit you a problem about clock generation. I have a 25MHz external clock driving a hardware block inside the FPGA. I need a 10MHz clock to drive another hardware block inside the same FPGA. How can I have a 10Mhz clock from the 25Mhz clock ? Is it possible ?

Your answers will be appreciated

Best Regards

/Alessandro Strazzero

Reply to
alessandro.strazzero
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Hi,

yes you can do that. I would suggest to study this document

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and in degeral read about DCM's if it a Xilinx chip, or check for PLL (sysClock pll's) for other vendors. Regards Alex

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Alex
Reply to
Alex

depending on the FPGA vendor, there are PLLs or DCMs that you can use. That is, applying a fractiponal rate of 2/5 gives you 10 MHz = 25 MHz * (2 /

5)

Vladislav

Reply to
Vladislav Muravin

Alessandro,

The CLKDV output of the Spartan or Virtex DCM may be used with DIV=2.5 to synchronously divide a 25 MHzz clock input to create a 10 MHz clock output.

Austin

Reply to
Austin Lesea

You might want to look in the FAQ:

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=================== Philip Freidin snipped-for-privacy@fpga-faq.org Host for

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Reply to
Philip Freidin

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