Dear everybody,
I'm a beginner in using VHDL to build hardware blocks. So, I would like to submit you a problem about clock generation. I have a 25MHz external clock driving a hardware block inside the FPGA. I need a 10MHz clock to drive another hardware block inside the same FPGA. How can I have a 10Mhz clock from the 25Mhz clock ? Is it possible ?
Your answers will be appreciated
Best Regards
/Alessandro Strazzero
Hi,
yes you can do that. I would suggest to study this document
depending on the FPGA vendor, there are PLLs or DCMs that you can use. That is, applying a fractiponal rate of 2/5 gives you 10 MHz = 25 MHz * (2 /
5)Vladislav
Alessandro,
The CLKDV output of the Spartan or Virtex DCM may be used with DIV=2.5 to synchronously divide a 25 MHzz clock input to create a 10 MHz clock output.
Austin
You might want to look in the FAQ:
=================== Philip Freidin snipped-for-privacy@fpga-faq.org Host for
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