Latest threads in Field-Programmable Gate Arrays

Why some firmware is made by lattice's FPGA instead of C language?

Regards: Why some firmware is made by lattice's FPGA instead of C language? Thank You. Best Regards to you all.

1 21yrs

mikelinyoho

1 21yrs mikelinyoho

Verilog translation

Hallo, what is the syntax to write in Verilog the following vhdl code? architecture IMP of user_logic is component clk1...

2 21yrs

marcotoschi

2 21yrs marcotoschi

What is the diffrences between lattice's FPGA and Xilinx's FPGA

Regards: What is the diffrences between lattice's FPGA and Xilinx's FPGA Thank You. Best Regards to you all.

3 21yrs

mikelinyoho

3 21yrs mikelinyoho

Could you tell me some other good forums or website related?

Hi, I am a new here. Also, a new to start learning FPGA. Could you tell me more good forums or website related to FPGA T...

2 21yrs

xfling2003

2 21yrs xfling2003

Kingston module structure

I have inherited a nearly-working FPGA SDRAM controller but my testing shows I have got the structure wrong, partly due...

2 21yrs

jms019

2 21yrs jms019

USB Blaster

Does anybody know how to program access to the Altera USB Blaster? I am trying to port Altera's SRunner software, which...

1 21yrs

jschamba

1 21yrs jschamba

Best FPGA for floating point performance

Hello, Does anybody already made a comparison of the high performance FPGA (Stratix II, V4, ?) relative to double preci...

12 21yrs

Marc.Battyani

12 21yrs Marc.Battyani

PLL

Hi Guys i am working on the image processing side and i wanted to impliment a function on the APEX20KE device and the c...

2 21yrs

vryaag

2 21yrs vryaag

looking for OLD OLD software

Hello all ... I know this is an odd request, but i'm looking for some old xilinx software to program some xilinx xc3000...

1 21yrs

cbeg

1 21yrs cbeg

Download bit stream onto ml310 ( virtex 2 pro ) using uart cable

Hello, I am using Xilinx EDK 7.1 and ml310 development board from Xilinx. I have fedora core 2 OS on my PC. I have prob...

2 21yrs

nitesh.guinde

2 21yrs nitesh.guinde

DDR memory writing all data twice & IPIF questions

I am modifying the Xilinx DDR controller core that comes with the EDK, changing it interface from IPIF to another inter...

0 21yrs

zoinks

0 21yrs zoinks

XST Help - Device Utilization Woes

Hello, I'm synthesizing a design in XST and I'm having a hard time figuring out what's consuming all of the devices res...

9 21yrs

killerhertz

9 21yrs killerhertz

Two microblaze in EDK

Hello! I'm trying on connecting two microblaze processors in EDK but I'm having problems. I used microblaze_bread_dataf...

4 21yrs

mvetromille

4 21yrs mvetromille

State Machine and BUFG

Hallo, I have made a state machine. When I synthetize it, XST adds lots of BUFG to states. My code: type state_type is...

7 21yrs

marcotoschi

7 21yrs marcotoschi

[Q] Synthesis : HowTo Preserve FSM encodings

Hi all, I just wonder if there is a possibility to add a constraint on the RTL level (VHDL/Verilog) to make shure that...

3 21yrs

meng.engineering

3 21yrs meng.engineering

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