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State Machine and BUFG

Hallo, I have made a state machine. When I synthetize it, XST adds lots of BUFG to states.

My code:

type state_type is ( seq_daq_state_1, seq_daq_state_2, seq_daq_state_3, seq_daq_state_4, seq_daq_state_5, seq_daq_state_6, seq_daq_state_7, seq_daq_state_8, seq_daq_state_9, seq_daq_state_10, seq_daq_state_11, seq_daq_state_12, seq_daq_state_13, seq_daq_state_14, seq_daq_state_15, seq_daq_state_16, seq_daq_state_17 );

signal seq_daq_state, seq_daq_next_state : state_type;

Here the log:

---------------------------------------------+---------------------------------------+-------+

Clock Signal | Clock buffer(FF name) | Load |

---------------------------------------------+---------------------------------------+-------+

USER_LOGIC_I__n0065(USER_LOGIC_I__n00651:O) | NONE(*)(USER_LOGIC_I_rx_data_received)| 1 |

USER_LOGIC_I__n0064(USER_LOGIC_I__n00641:O) | NONE(*)(USER_LOGIC_I_interrupt_0) | 1 |

OPB_Clk | BUFGP | 237 |

USER_LOGIC_I_Clk_Spi_I_prescaler_out:Q | BUFG | 7 |

USER_LOGIC_I_tx_state_FFd2:Q | NONE | 1 |

USER_LOGIC_I__n0062(USER_LOGIC_I__n00621:O) | NONE(*)(USER_LOGIC_I_interrupt_1) | 1 |

USER_LOGIC_I__n0221(USER_LOGIC_I__n0221183:O)| NONE(*)(USER_LOGIC_I_Adc_Mux_0) | 3 |

USER_LOGIC_I__n0060(USER_LOGIC_I__n00601:O) | NONE(*)(USER_LOGIC_I_Spi_Ss_0) | 1 |

USER_LOGIC_I__n0059(USER_LOGIC_I__n00591:O) | NONE(*)(USER_LOGIC_I_interrupt_2) | 1 |

USER_LOGIC_I__n0058(USER_LOGIC_I__n00581:O) | NONE(*)(USER_LOGIC_I_Spi_Ss_1) | 2 |

USER_LOGIC_I__n0057(USER_LOGIC_I__n00571:O) | NONE(*)(USER_LOGIC_I_interrupt_3) | 1 |

USER_LOGIC_I__n0056(USER_LOGIC_I__n00561:O) | NONE(*)(USER_LOGIC_I_interrupt_4) | 1 |

USER_LOGIC_I__n0055(USER_LOGIC_I__n00551:O) | NONE(*)(USER_LOGIC_I_interrupt_5) | 1 |

USER_LOGIC_I__n0054(USER_LOGIC_I__n00541:O) | NONE(*)(USER_LOGIC_I_interrupt_6) | 1 |

USER_LOGIC_I__n0053(USER_LOGIC_I__n00531:O) | NONE(*)(USER_LOGIC_I_interrupt_7) | 1 |

USER_LOGIC_I__n0052(USER_LOGIC_I__n00521:O) | NONE(*)(USER_LOGIC_I_tx_shift_enable) | 1 |

USER_LOGIC_I__n0051(USER_LOGIC_I__n00511:O) | NONE(*)(USER_LOGIC_I_rx_shift_enable) | 1 |

USER_LOGIC_I_seq_daq_state_FFd17:Q | BUFG | 16 |

USER_LOGIC_I_seq_daq_state_FFd15:Q | BUFG | 16 |

USER_LOGIC_I_seq_daq_state_FFd13:Q | BUFG | 16 |

USER_LOGIC_I_seq_daq_state_FFd11:Q | NONE | 16 |

USER_LOGIC_I_seq_daq_state_FFd9:Q | BUFG | 16 |

USER_LOGIC_I_seq_daq_state_FFd7:Q | BUFG | 16 |

USER_LOGIC_I_seq_daq_state_FFd5:Q | BUFG | 16 |

USER_LOGIC_I_seq_daq_state_FFd3:Q | NONE | 16 |

---------------------------------------------+---------------------------------------+-------+

(*) These 14 clock signal(s) are generated by combinatorial logic,

and XST is not able to identify which are the primary clock signals.

Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

In this way my project is overmapped, because it uses 10 GCLK.

In what way could I resolve this trouble?

There is a way to substitute BUFG with IBUF, in example?

Reply to
Marco
Loading thread data ...

Relevant is the code where you USE these signals. Obviously there's something wrong there.

BUFGs are inserted because XST has detected that some state signals are connected to clock inputs of Flipflops or other clocked components, hence it derives that these signals must be clocks.

I suggest you post a code snippet from your state machine, something's odd there.

cu, Sean

Reply to
Sean Durkin

SEQ_DAQ_SYNC_PROC: process ( BUS2IP_Clk, BUS2IP_Reset ) is begin

if ( BUS2IP_Reset = '1' ) then seq_daq_state

Reply to
Marco

ADC_MUX is a transparent latch controlled by seq_daq_state. Therefore synthesis treats seq_daq_state as a clock signal.

You need to either assign a value to ADC_MUX in all branches (including the case that seq_daq_state=seq_daq_state_4 and mux_channel(1)='1') or you to add an edge triggered DFF for ADC_MUX.

Kolja Sulimma

Marco schrieb:

Reply to
Kolja Sulimma

I have modified every state where I verify if mux_channel is '0' or '1' into the following:

when seq_daq_state_4 =>

Adc_Mux

Reply to
Marco

Get rid of the silly three-process state machine and make it all one or two clocked (synchronous) processes?

Reply to
Andy Peters

Marco,

I did not read the entire post, but I can tell you that:

(*) You have some latches in the design. (**) The instantiation you are looking is called BUFGP, but it includes IBUFG (clock pad) + BUFG (the actual clock buffer). using a general purpose I/O as clock is not good, since you will ge an error during the placement.

Vladislav

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Reply to
Vladislav Muravin

I have found the trouble, not Adc_Mux, but the assignment of the registers: slv_reg1, slv_reg2, ...

They are 8 registers of 16 bit datas.

I should realize a demultiplexer, but in a better way than the actual.

Any idea?

Reply to
Marco

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