Hallo, what is the syntax to write in Verilog the following vhdl code?
architecture IMP of user_logic is
component clk1440
port (
async_reset : in std_logic;
clock : in std_logic;
clock_enable : in std_logic;
output_50 : out std_logic;
output_pulse : out std_logic);
end component;
begin
--USER logic implementation added here
CLK_1440_I : clk1440
port map(
async_reset => BUS2IP_Reset,
clock => BUS2IP_Clk,
clock_enable => '1',
output_50 => lcd_cl_2_s,
output_pulse => Clock_En_s);
Many Thanks
Marco