I am modifying the Xilinx DDR controller core that comes with the EDK, changing it interface from IPIF to another interface I just completed some simulation runs and some things just don't seem right:
I created a PPC program that has a int pointer pointing at the DDR base address. Then a simple loop writes the same data to every address:
int* testfieldi = XPAR_DDR_SDRAM_32MX64_MEM0_BASEADDR;
int x; print("0"); // LOOP 1 for (x = 0; x < 20; x+=2) { testfieldi[x] = 0xDEADBAAF;
}But when I simulate this, the DDR controller always writes two neighbouring data's to the same address... I cannot check if there is any data actual corruption when I run it, I do not hava a physical board at hand.
Also the IPIF addressing looks kind of odd: The bus2IP addr gives a byte-aligned address, but there is also a byte-wise mask that is set as if the address given is 64 bit aligned. :
a byte write at address 1: bus2IP_addr: 0x1 bus2IP_be: 0x000000f0 a byte write at address 12: bus2IP_addr: 0x13 bus2IP_be: 0x00f00000
Anyone any thoughts about this one?