Field-Programmable Gate Arrays

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High baud rate chips for RS232 protocol

Hello all, I am interested in designing a custom board with serial interface and I am searching for RS232 port driver I...
6 comments posted 20yrs
posted by mansoor.naseer
6 comments posted 20yrs posted by mansoor.naseer

Modelling latches in Verilog

Hi, I'm trying to reimplement the design at in Verilog, targetting a Xilinx CPLD. Problem is, I've got all the GAL equa...
2 comments posted 20yrs
posted by philpem
2 comments posted 20yrs posted by philpem

The best way to sum 8 datas?

Hallo, which is the best way to sum 8 datas stored into a block ram? Many Thanks Marco Toschi
2 comments posted 20yrs
posted by marcotoschi
2 comments posted 20yrs posted by marcotoschi

Platform Cable USB

I'm using the ISE WebPack version and have just got a Platform USB cable. Could anyone give me a clue as to how I insta...
2 comments posted 21yrs
posted by enquiries
2 comments posted 21yrs posted by enquiries

Spartan 3 Ram Instantiation

Hey Folks, i have a question about the RAM instantiations for the Spartan 3(XC3S200) in the Xilinx verilog templates. Y...
8 comments posted 21yrs
posted by amir.intisar
8 comments posted 21yrs posted by amir.intisar

gal16v8 CUPL problems

Hi After searching more than 3 hours the web, awincupl.exe was found to compile some CUPL code. Personally I find it to...
1 comments posted 21yrs
posted by lathe_biosas
1 comments posted 21yrs posted by lathe_biosas

Creating higher bit multipliers from low bit.

Hello all Is there any algortihm by which i can combine 8 bit multipliers using adders and shifters to get 16 or 32 bit...
2 comments posted 21yrs
posted by vssumesh_asic
2 comments posted 21yrs posted by vssumesh_asic

XUP Virtex-II Pro "invalid target architecture"

I just installed and updated both the EDK and ISE 7.1 I'm using the XUP Virtex-II Pro, and downloaded the accompanying...
9 comments posted 21yrs
posted by zoinks
9 comments posted 21yrs posted by zoinks

Modelsim simulation question

Hallo, I'm simulating a peripheral into modelsim. I have watched some differences between: behavioral, post-translate,...
0 comments posted 21yrs
posted by marcotoschi
0 comments posted 21yrs posted by marcotoschi

Multidimensional port.

Hello all Is it possible to instantiate multi dimensional input/output port in verilog2001. I tried the following code....
3 comments posted 21yrs
posted by vssumesh_asic
3 comments posted 21yrs posted by vssumesh_asic

OT: CPLD - SimuCAD S/W CD

Hi All. First off - Apologies if anyone considers this not the place to post such information - but I am getting desper...
5 comments posted 21yrs
posted by spamless-news
5 comments posted 21yrs posted by spamless-news

I2C "SCL" line problem

Hi all, I faced the following problem with my I2C slave code(VHDL). I was incrementing a counter on the negative edge o...
6 comments posted 21yrs
posted by praveen.kantharajapura
6 comments posted 21yrs posted by praveen.kantharajapura

Xilinx and Lattice tools on one machine?

Does anyone have experience running tools from Xilinx (ISE, XST) and Lattice (ispLever) on the same Windows computer? I...
2 comments posted 21yrs
posted by gabor
2 comments posted 21yrs posted by gabor